ML145407RP データシートの表示（PDF） - LANSDALE Semiconductor Inc.
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ML145407RP Datasheet PDF : 8 Pages
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ML145407
LANSDALE Semiconductor, Inc.
17
19
VDD VCC
15
6
DI1 Tx1
13 DI2
Tx2 8
Vin = ± 2 V
11 DI3
Tx3 10
VSS GND
42
Rout
=
Vin
I
Figure 1. Power–Off Source Resistance
DRIVERS
DI1 – DI3
50%
tf
Tx1 – Tx3
90%
10%
tPHL
tPLH
3V
0V
tr
VOH
VOL
RECEIVERS
Rx1 – Rx3
50%
90%
DO1 – DO3
tPHL
50%
10%
tf
+3V
0V
tPLH
VOH
VOL
tr
Figure 2. Switching Characteristics
DRIVERS
3V
Tx1 – Tx3
–3V
tSLH
3V
–3V
tSHL
SLEW RATE (SR) = – 3 V – (3 V) OR 3 V – ( – 3 V)
tSLH
tSHL
Figure 3. Slew Rate Characterization
PIN DESCRIPTIONS
VCC
Digital Power Supply (Pin 19)
The digital supply pin, which is connected to the logic pow-
er supply. This pin should have a 0.33 µF capacitor to ground.
GND
Ground (Pin 2)
Ground return pin is typically connected to the signal ground
pin of the EIA–232–E connector (Pin 7) as well as to the logic
power supply ground.
VDD
Positive Power Supply (Pin 17)
This is the positive output of the on–chip voltage doubler and
the positive power supply input of the driver/receiver sections of
the device. This pin requires an external storage capacitor to fil-
ter the 50% duty cycle voltage generated by the charge pump.
VSS
Negative Power Supply (Pin 4)
This is the negative output of the on–chip voltage
doubler/inverter and the negative power supply input of the
driver/receiver sections of the device. This pin requires an
external storage capacitor to filter the 50% duty cycle voltage
generated by the charge pump.
C2+, C2–, C1–, C1+
Voltage Doubler and Inverter (Pins 1, 3, 18, 20)
These are the connections to the internal voltage doubler and
inverter, which generate the VDD and VSS voltages.
Rx1, Rx2, Rx3
Receive Data Input (Pins 5, 7, 9)
These are the EIA–232–E receive signal inputs. A voltage
between + 3 and + 25 V is decoded as a space and causes the
corresponding DO pin to swing to ground (0 V). A voltage
between – 3 and – 25 V is decoded as a mark, and causes the
DO pin to swing up to VCC.
DO1, DO2, DO3
Data Output (Pins 16, 14, 12)
These are the receiver digital output pins, which swing from
VCC to GND. Each output pin is capable of driving one
LSTTL input load.
DI1, DI2, DI3
Data Input (Pins 15, 13, 11)
These are the high impedance digital input pins to the driv-
ers. Input voltage levels on these pins must be between VCC
and GND.
Tx1, Tx2, Tx3
Transmit Data Output (Pins 6, 8, 10)
These are the EIA–232–E transmit signal output pins,which
swing toward VDD and VSS. A logic 1 at a DI input causes the
corresponding Tx output to swing toward VSS. A logic 0 caus-
es the output to swing toward VDD. The actual levels and slew
rate achieved will depend on the output loading (RL\\CL).
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