MU9C8358-QHC データシートの表示（PDF） - MUSIC Semiconductors
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MU9C8358-QHC Datasheet PDF : 32 Pages
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The Host Processor interface is asynchronous to the
System Clock. This interface is controlled by the /PCS or
/PCSS (whichever is appropriate) and PROC_RDY
signals, which form the handshaking between the
processor and the MU9C8358. This allows the end system
to use a processor that runs at a different clock speed than
the clock required by the MU9C8358. (see Timing
Diagrams: Timing Data for Host Processor Interface).
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Processor Chip Select is taken LOW by the host processor
to gain access to the MU9C8358 Port or Chip registers.
When two MU9C8358 devices are connected together,
each device should have its own independent /PCS signal.
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Processor Chip Select System is taken LOW by the host
processor to gain access to the MU9C8358 System
registers or to access the LANCAM. When two
MU9C8358 devices are connected together, the /PCSS
inputs should be connected together.
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Read/Write determines the direction of data flow into or
out of the MU9C8358 host processor interface. If /WRITE
is LOW, the data is written into the register selected by
A[7:0] and /PCS or /PCSS; if HIGH, the data is read from
the register selected by A[7:0] and /PCS or /PCSS.
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Processor Address bus A[7:0] selects the MU9C8358
register accessed by the host processor.
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Processor Data bus D[15:0] is the tri-state processor data
bus for the MU9C8358.
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When reading from or writing to any MU9C8358 internal
register, the PROC_RDY tri-state output goes LOW on the
falling edge of /PCS or /PCSS. It goes HIGH on the rising
edge of the first SYSCLK after /PCS or /PCSS is LOW, to
indicate that data is available (read) or data has been
accepted (write).
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/INTR goes LOW to signal that one of the four
configurable interrupt conditions have been satisfied. The
four separate conditions are configured by setting bits in
the appropriate register. /INTR returns HIGH when the
appropriate register is read. See Table 2 for details of
which interrupt conditions are possible and which register
must be read to reset the /INTR pin to HIGH.
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See Timing Diagrams: Timing Data for LANCAM
Interface.
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DQ[15:0] tri-state 16-bit bus transfers data or instructions
between the MU9C8358 and the LANCAM. When no
data or instructions are present on the bus, the bus goes
HIGH-Z.
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The /E chip enable is taken LOW to initiate LANCAM
activity. On LANCAM read cycles, /E is taken HIGH after
the MU9C8358 registers the data.
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The MU9C8358 outputs /W (read/write select) to control
the direction of data flow between the MU9C8358 and the
LANCAM. If /W is LOW at the falling edge of /E, the
MU9C8358 outputs data on the DQ[15:0] bus for the
LANCAM as input. When /W is HIGH at the falling edge
of /E, the LANCAM outputs data on the DQ[15:0] bus to
the MU9C8358 as input.
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The MU9C8358 outputs /CM Data/Command Select to
control whether the LANCAM interprets the DQ[15:0]
bus contents as command information or data. If both /CM
and /W are LOW at the falling edge of /E, the MU9C8358
outputs an instruction for the LANCAM to execute or a
value for one of the LANCAM configuration registers. If
/CM is LOW while /W is HIGH, then the LANCAM will
output data from one of its configuration registers to the
MU9C8358. If /CM is HIGH while /W is LOW, the
MU9C8358 will output data for the LANCAM to place in
one of its data registers or memory. If /CM is HIGH
while /W is HIGH, the LANCAM outputs data from one
of its data registers or memory to the MU9C8358.
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