ATF1500AS-15AC100 データシートの表示（PDF） - Atmel Corporation

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ATF1500AS-15AC100

High-Performance EE CPLD

Atmel Corporation 

ATF1504ASZ

load data into the update registers. Control signals are gen-

erated internally by the JTAG TAP controller. The BSC

configuration for the input and I/O pins and macrocells are

shown below.

BSC Configuration for Input and I/O

Pins (except JTAG TAP Pins)

BSC Configuration for Macrocell

Pin BSC

TDO

Pin

0

DQ

1

Capture

DR

TDI Clock

Shift

Note: The ATF1504AS has pull-up option on TMS and TDI

pins. This feature is selected as a design option.

OEJ

0

1

TDO

DQ

0

1

DQ

OUTJ

0

DQ

1

0

1

Pin

DQ

Capture

DR

Update

DR

TDI

Shift

Clock

Mode

Macrocell BSC

13

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