IDT70T651S12DRGI8 データシートの表示（PDF） - Integrated Device Technology
部品番号
コンポーネント説明
メーカー
IDT70T651S12DRGI8
Integrated Device Technology
IDT70T651S12DRGI8 Datasheet PDF : 28 Pages
| |||
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70T651/9S10
Com'l Only
70T651/9S12
Com'l
& Ind
70T651/9S15
Com'l Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address Access Time
tACE
Chip Enable Access Time(3)
tABE
Byte Enable Access Time(3)
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time(1,2)
tHZ
Output High-Z Time(1,2)
tPU
Chip Enable to Power Up Time(2)
tPD
Chip Disable to Power Down Time(2)
tSOP
Semaphore Flag Update Pulse (OE or SEM)
10
____
12
____
15
____
ns
____
10
____
12
____
15
ns
____
10
____
12
____
15
ns
____
5
____
6
____
7
ns
____
5
____
6
____
7
ns
3
____
3
____
3
____
ns
0
____
0
____
0
____
ns
0
4
0
6
0
8
ns
0
____
0
____
0
____
ns
____
8
____
8
____
12
ns
____
4
____
6
____
8
ns
tSAA
Semaphore Address Access Time
2
10
2
12
2
15
ns
5632tbl 12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(4)
70T651/9S10
Com'l Only
70T651/9S12
Com'l
& Ind
70T651/9S15
Com'l Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
tWC
Write Cycle Time
10
____
12
____
15
____
ns
tEW
Chip Enable to End-of-Write(3)
8
____
10
____
12
____
ns
tAW
Address Valid to End-of-Write
8
____
10
____
12
____
ns
tAS
Address Set-up Time(3)
0
____
0
____
0
____
ns
tWP
Write Pulse Width
8
____
10
____
12
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
6
____
8
____
10
____
ns
tDH
Data Hold Time(4)
0
____
0
____
0
____
ns
tWZ
Write Enable to Output in High-Z(1,2)
tOW
Output Active from End-of-Write(1,2,4)
____
4
____
6
____
8
ns
0
____
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
NOTES:
5632 tbl 13
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when
CE0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
5. 10nsIndustrialspeedgradeisavailableinBF-208andBC-256packagesonly.
11
Share Link: