IDT70T651S12DRGI8 データシートの表示（PDF） - Integrated Device Technology

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IDT70T651S12DRGI8

HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

Integrated Device Technology 

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)

Symbol

|ILI|

|ILI|

|ILO|

VOL (3.3V)

VOH (3.3V)

VOL (2.5V)

VOH (2.5V)

Parameter

Input Leakage Current(1)

JTAG & ZZ Input Leakage Current(1,2)

Output Leakage Current(1,3)

Output Low Voltage(1)

Output High Voltage(1)

Output Low Voltage(1)

Output High Voltage(1)

Test Conditions

VDDQ = Max., VIN = 0V to VDDQ

VDD = Max., VIN = 0V to VDD

CE0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ

IOL = +4mA, VDDQ = Min.

IOH = -4mA, VDDQ = Min.

IOL = +2mA, VDDQ = Min.

IOH = -2mA, VDDQ = Min.

NOTES:

1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details.

2. Applicable only for TMS, TDI and TRST inputs.

3. Outputs tested in tri-state mode.

70T651/9S

Min.

Max.

___

10

___

+30

___

10

___

0.4

2.4

___

___

0.4

2.0

___

Unit

µA

µA

µA

V

V

V

V

5632 tbl 09

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(3) (VDD = 2.5V ± 100mV)

70T651/9S10

Com'l

& Ind(7)

70T651/9S12

Com'l

& Ind

70T651/9S15

Com'l Only

Symbol

Parameter

Test Condition

Version Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Unit

IDD Dynamic Operating CEL and CER= VIL,

Current (Both

Outputs Disabled

Ports Active)

f = fMAX(1)

COM'L S 300 405 300 355 225 305 mA

IND

S 300 445 300 395

____

____

ISB1(6)

Standby Current

(Both Ports - TTL

Level Inputs)

CEL = CER = VIH

f = fMAX(1)

COM'L S 90

120

75

105

60

85 mA

IND

S 90

145

75

130

____

____

ISB2(6)

Standby Current

(One Port - TTL

Level Inputs)

CE"A" = VIL and CE"B" = VIH(5)

Active Port Outputs Disabled,

f = fMAX(1)

COM'L S 200 265 180 230 150 200 mA

IND

S 200 290 180 255

____

____

ISB3 Full Standby Current Both Ports CEL and

(Both Ports - CMOS CER > VDDQ - 0.2V,

COM'L S 2

10

2

10

2

10 mA

Level Inputs)

VIN > VDDQ - 0.2V or VIN < 0.2V,

f = 0(2)

IND

S2

20

2

20

____

____

ISB4(6)

Full Standby Current

(One Port - CMOS

Level Inputs)

CE"A" < 0.2V and

CE"B" > VDDQ - 0.2V(5)

VIN > VDDQ - 0.2V or VIN < 0.2V,

Active Port, Outputs Disabled,

f = fMAX(1)

COM'L S 200

265

180

230

150

200 mA

IND

S 200 290 180 255

____

____

IZZ Sleep Mode Current ZZL = ZZR = VIH

(Both Ports - TTL

f = fMAX(1)

Level Inputs)

COM'L S 2

10

2

10

2

10 mA

IND

S2

20

2

20

____

____

5632 tbl 10

NOTES:

1. Atf=fMAX,addressandcontrollines(exceptOutputEnable)arecyclingatthemaximumfrequencyreadcycleof1/tRC,using"ACTESTCONDITIONS"atinputlevels

of GND to 3.3V.

2. f=0meansnoaddressorcontrollineschange.AppliesonlytoinputatCMOSlevelstandby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDDDC(f=0)= 100mA (Typ).

5. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V

CEX > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X < 0.2V.

"X" represents "L" for left port or "R" for right port.

6. ISB1,ISB2andISB4will all reach full standby levels (ISB3)ontheappropriateport(s)ifZZLand/orZZR= VIH.

7. 10nsIndustrialspeedgradeisavailableinBF-208andBC-256packagesonly.

9

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