IDT71V321L データシートの表示（PDF） - Integrated Device Technology

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IDT71V321L

HIGH SPEED 3.3V 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

Integrated Device Technology 

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Timing Waveform of Write with BUSY(3)

tWP

R/W"A"

Industrial and Commercial Temperature Ranges

BUSY"B"

R/W"B"

tWH (1)

,

(2)

NOTES:

1. tWH mustbemetfor BUSYoutput71V321.

2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.

3. Alltimingisthesamefortheleftandrightports.Port"A"maybeeithertheleftorrightport.Port"B"isoppositefromport"A".

3026 drw 11

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

ADDR

"A" AND "B"

ADDRESSES MATCH

CE"B"

CE"A"

BUSY"A"

tAPS(2)

tBAC

tBDC

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Timing Waveform of BUSY Arbitration Controlled

by Address Match Timing(1)

ADDR"A"

ADDR"B"

tAPS (2)

tRC OR tWC

ADDRESSES MATCH

ADDRESSES DO NOT MATCH

BUSY"B"

tBAA

tBDA

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. IftAPSisnotsatisfied,theBUSY willbeassertedononesideortheother,butthereisnoguaranteeonwhichside BUSYwillbeasserted.

3026 drw 13

61.402

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