M58CR064C データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

メーカー

M58CR064C

64 Mbit (4Mb x 16, Dual Bank, Burst) 1.8V Supply Flash Memory

STMicroelectronics 

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Code for flowcharts for using the Program/Erase

Resume command.

Protection Register Program Command

The Protection Register Program command is

used to Program the 128 bit user One-Time-Pro-

grammable (OTP) segment of the Protection Reg-

ister. The segment is programmed 16 bits at a

time. When shipped all bits in the segment are set

to ‘1’. The user can only program the bits to ‘0’.

Two write cycles are required to issue the Protec-

tion Register Program command.

s The first bus cycle sets up the Protection

Register Program command.

s The second latches the Address and the Data to

be written to the Protection Register and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started.

The segment can be protected by programming bit

1 of the Protection Lock Register. Bit 1 of the Pro-

tection Lock Register also protects bit 2 of the Pro-

tection Lock Register. Programming bit 2 of the

Protection Lock Register will result in a permanent

protection of Parameter Block #0 (see Figure 5,

Security Block and Protection Register Memory

Map). Attempting to program a previously protect-

ed Protection Register will result in a Status Reg-

ister error. The protection of the Protection

Register and/or the Security Block is not revers-

ible.

The Protection Register Program cannot be sus-

pended. See Appendix C, Figure 27, Protection

Register Program Flowchart and Pseudo Code,

for a flowchart for using the Protection Register

Program command.

Set Configuration Register Command.

The Set Configuration Register command is used

to write a new value to the Configuration Control

Register which defines the burst length, type, X la-

tency, Synchronous/Asynchronous Read mode

and the valid Clock edge configuration.

Two Bus Write cycles are required to issue the Set

Configuration Register command.

s The first cycle writes the setup command and

the address corresponding to the Configuration

Register content.

s The second cycle writes the Configuration

Register data and the confirm command.

Once the command is issued the memory returns

to Read mode.

The value for the Configuration Register is always

presented on A0-A15. CR0 is on A0, CR1 on A1,

etc.; the other address bits are ignored.

Block Lock Command

The Block Lock command is used to lock a block

and prevent Program or Erase operations from

changing the data in it. All blocks are locked at

power-up or reset.

Two Bus Write cycles are required to issue the

Block Lock command.

s The first bus cycle sets up the Block Lock

command.

s The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 13 shows the Lock Status after issuing a

Block Lock command.

The Block Lock bits are volatile, once set they re-

main set until a hardware reset or power-down/

power-up. They are cleared by a Block Unlock

command. Refer to the section, Block Locking, for

a detailed explanation. See Appendix C, Figure

26, Locking Operations Flowchart and Pseudo

Code, for a flowchart for using the Lock command.

Block Unlock Command

The Block Unlock command is used to unlock a

block, allowing the block to be programmed or

erased. Two Bus Write cycles are required to is-

sue the Block Unlock command.

s The first bus cycle sets up the Block Unlock

command.

s The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table 13 shows the protection status after issuing

a Block Unlock command. Refer to the section,

Block Locking, for a detailed explanation and Ap-

pendix C, Figure 26, Locking Operations Flow-

chart and Pseudo Code, for a flowchart for using

the Unlock command.

Block Lock-Down Command

A locked or unlocked block can be locked-down by

issuing the Block Lock-Down command. A locked-

down block cannot be programmed or erased, or

have its protection status changed when WP is

low, VIL. When WP is high, VIH, the Lock-Down

function is disabled and the locked blocks can be

individually unlocked by the Block Unlock com-

mand.

Two Bus Write cycles are required to issue the

Block Lock-Down command.

s The first bus cycle sets up the Block Lock

command.

s The second Bus Write cycle latches the block

address.

15/70

Share Link: