M58CR064D データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

メーカー

M58CR064D

64 Mbit (4Mb x 16, Dual Bank, Burst) 1.8V Supply Flash Memory

STMicroelectronics 

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

s The third bus cycle latches the Address and the

Data of the second word to be written.

s The fourth bus cycle latches the Address and

the Data of the third word to be written.

s The fifth bus cycle latches the Address and the

Data of the fourth word to be written and starts

the Program/Erase Controller.

Read operations to the bank being programmed

output the Status Register content after the pro-

gramming has started.

Programming aborts if Reset goes to VIL. As data

integrity cannot be guaranteed when the program

operation is aborted, the memory locations must

be reprogrammed.

During Quadruple Word Program operations the

bank being programmed will only accept the Read

Status Register command, all other commands

will be ignored.

Dual operations are not supported during Quadru-

ple Word Program operations. It is not recom-

mended to suspend the Quadruple Word Program

command. Typical Program times are given in Ta-

ble 14, Program, Erase Times and Program/Erase

Endurance Cycles.

See Appendix C, Figure 22, Quadruple Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Quadruple Word Program

command.

Table 7. Factory Program Commands

Bus Write Operations

Command Phase

1st

2nd

3rd

4th

Add Data Add Data Add Data Add Data

Bank Erase

2 BKA

80h

BKA D0h

Double Word Program(2)

3 BKA

30h WA1 PD1 WA2 PD2

Quadruple Word

Program(3)

5 BKA 55h WA1 PD1 WA2 PD2 WA3 PD3

Note: 1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, WA1 is the Start Address.

2. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0.

3. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

5th

Add Data

WA4 PD4

19/70

Share Link: