M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 6. X-Latency and Data Output Configuration Example
X-latency
1st cycle
2nd cycle
3rd cycle
4th cycle
K
E
L
A21-A0
tDELAY
VALID ADDRESS
tAVK_CPU
DQ15-DQ0
tACC
tQVK_CPU
tK
tKQV
tQVK_CPU
VALID DATA VALID DATA
Note. Settings shown: X-latency = 4, Data Output held for one clock cycle
Figure 7. Wait Configuration Example
AI90005
E
K
L
A21-A0
DQ15-DQ0
WAIT
CR8 = '0'
WAIT
CR8 = '1'
VALID ADDRESS
VALID DATA VALID DATA NOT VALID VALID DATA
AI90006b
25/70