M58CR064D データシートの表示（PDF） - STMicroelectronics

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M58CR064D

64 Mbit (4Mb x 16, Dual Bank, Burst) 1.8V Supply Flash Memory

STMicroelectronics 

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

READ MODES

Read operations can be performed in two different

ways depending on the settings in the Configura-

tion Register. If the clock signal is ‘don’t care’ for

the data output, the read operation is Asynchro-

nous; if the data output is synchronized with clock,

the read operation is Synchronous.

The Read mode and data output format are deter-

mined by the Configuration Register. (See Config-

uration Register section for details). All banks

supports both asynchronous and synchronous

read operations. The Dual Bank architecture al-

lows read operations in one bank, while write op-

erations are being executed in the other (see

Tables 11 and 12).

Asynchronous Read Mode

In Asynchronous Read operations the clock signal

is ‘don’t care’. The device outputs the data corre-

sponding to the address latched, that is the mem-

ory array, Status Register, Common Flash

Interface or Electronic Signature depending on the

command issued. CR15 in the Configuration Reg-

ister must be set to ‘1’ for Asynchronous opera-

tions.

In Asynchronous Read mode a Page of data is in-

ternally read and stored in a Page Buffer. The

Page has a size of 4 Words and is addressed by

A0 and A1 address inputs. The address inputs A0

and A1 are not gated by Latch Enable in Asyn-

chronous Read mode.

The first read operation within the Page has a

longer access time (Tacc, Random access time),

subsequent reads within the same Page have

much shorter access times. If the Page changes

then the normal, longer timings apply again.

Asynchronous Read operations can be performed

in two different ways, Asynchronous Random Ac-

cess Read and Asynchronous Page Read. Only

Asynchronous Page Read takes full advantage of

the internal page storage so different timings are

applied.

See Table 20, Asynchronous Read AC Character-

istics, Figure 10, Asynchronous Random Access

Read AC Waveform and Figure 11, Asynchronous

Page Read AC Waveform for details.

Synchronous Burst Read Mode

In Synchronous Burst Read mode the data is out-

put in bursts synchronized with the clock. It is pos-

sible to perform burst reads across bank

boundaries.

Synchronous Burst Read mode can only be used

to read the memory array. For other read opera-

tions, such as Read Status Register, Read CFI

and Read Electronic Signature, Single Synchro-

nous Read or Asynchronous Random Access

Read must be used.

In Synchronous Burst Read mode the flow of the

data output depends on parameters that are con-

figured in the Configuration Register.

A burst sequence is started at the first clock edge

(rising or falling depending on Valid Clock Edge bit

CR6 in the Configuration Register) after the falling

edge of Latch Enable or Chip Enable, whichever

occurs last. Addresses are internally incremented

and after a delay of 2 to 5 clock cycles (X latency

bits CR13-CR11) the corresponding data are out-

put on each clock cycle.

The number of Words to be output during a Syn-

chronous Burst Read operation can be configured

as 4 or 8 Words or Continuous (Burst Length bits

CR2-CR0). The data can be configured to remain

valid for one or two clock cycles (Data Output Con-

figuration bit CR9).

The order of the data output can be modified

through the Burst Type and the Wrap Burst bits in

the Configuration Register. The burst sequence

may be configured to be sequential or interleaved

(CR7). The burst reads can be confined inside the

4 or 8 Word boundary (Wrap) or overcome the

boundary (No Wrap). If the starting address is

aligned to the Burst Length (4 or 8 Words), the

wrapped configuration has no impact on the output

sequence. Interleaved mode is not allowed in Con-

tinuous Burst Read mode or with No Wrap se-

quences.

A WAIT signal may be asserted to indicate to the

system that an output delay will occur. This delay

will depend on the starting address of the burst se-

quence; the worst case delay will occur when the

sequence is crossing a 64 word boundary and the

starting address was at the end of a four word

boundary.

WAIT is asserted during the Wait state and at the

end of 4- and 8-Word Burst. It is deasserted during

the X latency and when output data are valid. In

Continuous Burst Read mode a Wait state will oc-

cur when crossing the first 64 Word boundary. If

the burst starting address is aligned to a 4 Word

Page, the Wait state will not occur.

The WAIT signal is active Low. The WAIT signal is

meaningful only in Synchronous Burst Read

mode, in other modes, WAIT is not asserted (ex-

cept for Read Array mode).

See Table 21, Synchronous Read AC Character-

istics and Figure 12, Synchronous Burst Read AC

Waveform for details.

Single Synchronous Read Mode

Single Synchronous Read operations are similar

to Synchronous Burst Read operations except that

only the first data output after the X latency is valid.

Other Configuration Register parameters have no

effect on Single Synchronous Read operations.

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