ST72141K2-AUTO データシートの表示（PDF） - STMicroelectronics

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ST72141K2-AUTO

8-bit MCU for automotive with electric-motor control, ADC, 16-bit timers, SPI interface

STMicroelectronics 

ST72141K2-Auto

3.4 RESET MANAGER

The RESET block includes three RESET sources

as shown in Figure 10:

– External RESET source pulse

– Internal LVD RESET (Low Voltage Detection)

– Internal WATCHDOG RESET

Figure 10. Reset Block Diagram

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

A 4096 CPU clock cycle delay allows the oscillator

to stabilize and ensures that recovery has taken

place from the Reset state.

The RESET vector fetch phase duration is 2 clock

cycles.

RESET

VDD

RON

fCPU

INTERNAL

RESET

WATCHDOG RESET

LVD RESET

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