AD9870 データシートの表示（PDF） - Analog Devices
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AD9870 Datasheet PDF : 20 Pages
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AD9870
The recommended setting for LOFA is LOR/16. Choosing a
larger value for LOFA will increase T. Thus, for a given phase
difference between the LO input and the fREF input, the instan-
taneous charge pump current will be less than that available for
a LOFA value of LOR/16. Similarly, a smaller value for LOFA
will decrease T, making more current available for the same
phase difference. In other words, a smaller value of LOFA will
enable the synthesizer to settle faster in response to a frequency
hop than will a large LOFA value. Care must be taken to choose
a value of LOFA which is large enough (values greater than four
recommended) to prevent the loop from oscillating back and
forth in response to a frequency hop.
Table V. SPI Registers Associated with LO Synthesizer
Address Bit
(Hex) Breakdown Width
0x00
(7:0)
8
0x08
(5:0)
6
0x09
(7:0)
8
0x0A (7:5)
3
(4:0)
5
0x0B (7:0)
8
0x0C (6)
1
(5)
1
(4:2)
3
(1:0)
2
0x0D (3:0)
4
0x0E (7:0)
8
Default Value Name
0xFF
0x00
0x38
0x5
0x00
0x1D
0
0
0
0
0x0
0x04
STBY
LOR(13:8)
LOR(7:0)
LOA
LOB(12:8
LOB(7:0)
LOF
LOINV
LOI
LOTM
LOFA(13:8)
LOFA(7:0)
CLOCK SYNTHESIZER
The clock synthesizer is a fully programmable integer-N PLL
capable of 2.2 kHz resolution at clock input frequencies up to
18 MHz and reference frequencies up to 25 MHz. It is similar
to the LO synthesizer described previously in Figure 4 with the
following exceptions:
• It does not include an 8/9 prescaler nor an A Counter.
• It includes a negative-resistance core which when used in
conjunction with an external varactor serves as the VCO.
The 14-bit reference counter and 13-bit N-divider counter can
be programmed via the following registers: CKR and CKN. The
charge pump current is programmable via the CKI register
from 0.625 mA to 5.0 mA using the following equation:
IPUMP = (CKI + 1) × 0.625 mA.
The fast acquire subcircuit of the charge pump is controlled by
the CKFA register in the same manner as the LO synthesizer is
controlled by the LOFA register. An on-chip lock detect func-
tion (enabled by the CKF bit) automatically increases the output
current for faster settling during channel changes. The synthe-
sizer may also be disabled using the CKOB standby bit located
in the STBY register.
LOOP
FILTER
RD
COSC
CVAR
LOSC
VDDC=3.0 V
RBIAS
0.1F
IOUTC
AD9870
CLKP
CLKN
VCM = VDDC – RBIAS ؋ IBIAS > 1.6V
fOSC > (2 ؋ LOSC ؋(C VARACTOR//COSC))–1/2
CLK OSC. BIAS
2
IBIAS = 0.25, 0.35,
0.53, OR 0.85 mA
Figure 6. External Loop Filter, Varactor and L-C Tank Are
Required to Realize a Complete Clock Synthesizer
The AD9870 clock synthesizer circuitry includes a negative-
resistance core so that only an external L-C tank circuit with a
varactor is needed to realize a voltage controlled oscillator (VCO).
Figure 6 shows the external components required to complete
the clock synthesizer along with the equivalent input of the CLK
input. The resonant frequency of the VCO is approximately deter-
mined by LOSC and the series equivalent capacitance of COSC and
CVAR. As a result, LOSC, COSC, and CVAR should be selected to
provide sufficient tuning range to ensure proper locking of the
clock synthesizer The bias, IBIAS, of the negative-resistance core
has four programmable settings. Lower equivalent Q of the L-C
tank circuit may require a higher bias setting of the negative-
resistance core to ensure proper oscillation. RBIAS should be
selected such that the common-mode voltage at CLKP and
CLKN is approximately 1.6 V. The synthesizer may be disabled
via the CK standby bit to allow the user to employ an external
synthesizer and/or VCO in place of those resident on the IC.
Table VI. SPI Registers Associated with CLK Synthesizer
Address
(Hex)
0x00
0x01
0x10
0x11
0x12
0x13
0x14
0x15
0x16
Bit
Breakdown Width
(7:0)
8
(3:2)
2
(5:0)
6
(7:0)
8
(4:0)
5
(7:0)
8
(6)
1
(5)
1
(4:2)
3
(1:0)
1
(3:0)
4
(7:0)
8
Default Value Name
0xFF
0
00
0x38
0x00
0x3C
0
0
0
0
0x0
0x04
STBY
CKOB
CKR(13:8)
CKR(7:0)
CKN(12:8)
CKN(7:0)
CKF
CKINV
CKI
CKTM
CKFA(13:8)
CKFA(7:0)
REV. 0
–11–
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