UPD70433GJ-16-3EB データシートの表示（PDF） - NEC => Renesas Technology

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UPD70433GJ-16-3EB

V55PI™ 16-BIT MICROPROCESSOR

NEC => Renesas Technology 

µPD70433

However, using a segment override prefix instruction makes it possible for access of general variables to change from

DS0 to another segment register. Also, in addressing which uses BP as the base register, another segment register can

be used instead of SS.

Example

MOV

MOV

MOV

AW, 1000H

DS1 : AW

BL, DS1, BYTE PTR [IX]; DSI : Byte data read from IX

When a reset is performed, PS of register bank 15 is initialized to FFFFH, and SS, DS0 and DS1 are initialized to 0000H.

These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding

the offset for each register to (register bank number × 32).

Table 3-3. Segment Register Offsets

Register

DS0

DS1

SS

PS

Offset

08H

0EH

0AH

0CH

3.2.5 Extended Segment Registers (DS2, DS3)

In addition to the segment registers for accessing the 1M-byte basic memory space, the V55PI is provided with extended

segment registers which specify the start address of each 64K-byte segment of the 16M-byte extended memory space.

There are two extended segment registers, DS2 (Data Segment 2) and DS3 (Data Segment 3), which are used as shown

below.

DS2: Extended memory space general variable accesses (by segment override prefix instructions), source block

data accesses in extended memory space block transfer instructions, etc.

DS3: Extended memory space general variable accesses (by segment override prefix instructions), destination

block data accesses in extended memory space block transfer instructions, etc.

The data access using an extended semgnet register is performed by using the segment override prefix. Especially, in

the block transfer instruction, DS2 and DS3 can be specified simultaneously by segment override prefix. (In this case, the

order for DS2 and DS3 is optional.)

Example

REP

DS2:

DS3: MOVBKW ; Word memory block transfer from DS2 : IX to DS3 : IY.

The CPU specifies the start address of each segment with an extended segment register, and performs an access by

using another register or effective address for the specification of physical address, with the relative address from the start

address as the offset value.

The physical address is created as shown in the next page.

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