MAX6874 データシートの表示（PDF） - Maxim Integrated

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MAX6874

EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors

Maxim Integrated 

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

For the configuration EEPROM, valid address pointers

range from 8000h to 8045h. Registers 8046h to 804Fh

are reserved and should not be overwritten. Register

addresses from 8050h to 80FFh return a NACK from

the MAX6874/MAX6875. When using the block write

protocol, the address pointer automatically increments

after each data byte, except when the address pointer

is already at 8045h. If the address pointer is already

8045h, and more data bytes are being sent, these sub-

sequent bytes overwrite address 8045h repeatedly,

leaving only the last data byte sent stored at this regis-

ter address.

For the user EEPROM, valid address pointers range

from 8100h to 81FFh and 8200h to 82FFh. Block write

and block read protocols allow the address pointer to

reset (to 8100h or 8200h) when attempting to write or

read beyond 81FFh or 82FFh.

Configuration EEPROM

The configuration EEPROM addresses range from 8000h

to 8045h. Write data to the configuration EEPROM to

automatically set up the MAX6874/MAX6875 upon power-

up. Data transfers from the configuration EEPROM to the

configuration registers when ABP exceeds UVLO during

power-up or after a software reboot. After ABP exceeds

UVLO, an internal 1MHz clock starts after a 5µs delay,

and data transfer begins. Data transfer disables access

to the configuration registers and EEPROM. The data

transfer from EEPROM to configuration registers takes

3.5ms (max). Read configuration EEPROM data at any

time after power-up or software reboot. Write commands

to the configuration EEPROM are allowed at any time

after power-up or software reboot, unless the configura-

tion lock bit is set (see Table 20). The maximum cycle

time to write a single byte is 11ms (max).

User EEPROM

The 512 byte user EEPROM addresses range from

8100h to 82FFh (see Figure 7). Store software-revision

data, board-revision data, and other data in these reg-

isters. The maximum cycle time to write a single byte is

11ms (max).

Configuration Register Bank and EEPROM

The configuration registers can be directly modified by

the serial interface without modifying the EEPROM after

the power-up procedure terminates and the configura-

tion EEPROM data has been loaded into the configura-

tion register bank. Use the write byte or block write

protocols to write directly to the configuration registers.

Changes to the configuration registers take effect

immediately and are lost upon power removal.

At device power-up, the register bank loads configura-

tion data from the EEPROM. Configuration data may be

directly altered in the register bank during application

development, allowing maximum flexibility. Transfer the

new configuration data, byte by byte, to the configura-

tion EEPROM with the write byte protocol. The next

device power-up or software reboot automatically loads

the new configuration.

Table 17. Register Map

REGISTER

ADDRESS

EEPROM

MEMORY

ADDRESS

00h

8000h

01h

8001h

02h

8002h

03h

8003h

04h

8004h

05h

8005h

06h

8006h

07h

8007h

08h

8008h

09h

8009h

0Ah

800Ah

READ/

WRITE

DESCRIPTION

R/W IN1 undervoltage detector threshold (Table 2).

R/W IN2 undervoltage detector threshold (Table 3).

R/W IN3 undervoltage detector threshold (Table 4).

R/W IN4 undervoltage detector threshold (Table 4).

R/W IN5 undervoltage detector threshold (MAX6874 only) (Table 4).

R/W IN6 undervoltage detector threshold (MAX6874 only) (Table 4).

—

Not used.

—

Not used.

—

Not used.

—

Not used.

—

Not used.

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