MAX6884 データシートの表示（PDF） - Maxim Integrated

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MAX6884

EEPROM-Programmable, Hex Power-Supply Supervisory Circuits

Maxim Integrated 

EEPROM-Programmable, Hex

Power-Supply Supervisory Circuits

Start and Stop Conditions

Both SCL and SDA idle high when the bus is not busy. A

master device signals the beginning of a transmission

with a START (S) condition (see Figure 8) by transitioning

SDA from high to low while SCL is high. The master

device issues a STOP (P) condition (see Figure 8) by

transitioning SDA from low to high while SCL is high. A

STOP condition frees the bus for another transmission.

The bus remains active if a REPEATED START condition

is generated, such as in the block read protocol (see

Figure 11).

Early STOP Conditions

The MAX6884/MAX6885 recognize a STOP condition at

any point during transmission except if a STOP condition

occurs in the same high pulse as a START condition.

This condition is not a legal I2C format; at least one clock

pulse must separate any START and STOP condition.

Repeated START Conditions

A REPEATED START (SR) condition may indicate a

change of data direction on the bus. Such a change

occurs when a command word is required to initiate a

read operation (see Figure 11). SR may also be used

when the bus master is writing to several I2C devices

and does not want to relinquish control of the bus. The

MAX6884/MAX6885 serial interface supports continu-

ous write operations with or without an SR condition

separating them. Continuous read operations require

SR conditions because of the change in direction of

data flow.

Acknowledge

The acknowledge bit (ACK) is the 9th bit attached to any

8-bit data word. The receiving device always generates

an ACK. The MAX6884/MAX6885 generate an ACK

when receiving an address or data by pulling SDA low

during the 9th clock period (see Figure 9). When trans-

mitting data, such as when the master device reads data

back from the MAX6884/MAX6885, the MAX6884/

MAX6885 wait for the master device to generate an ACK.

Monitoring ACK allows for detection of unsuccessful

data transfers. An unsuccessful data transfer occurs if

the receiving device is busy or if a system fault has

occurred. In the event of an unsuccessful data transfer,

the bus master should reattempt communication at a

later time. The MAX6884/MAX6885 generate a NACK

after the command byte during a software reboot, while

writing to the EEPROM, or when receiving an illegal

memory address.

Slave Address

The MAX6884/MAX6885 slave address conforms to the

following table:

SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0

(MSB)

(LSB)

1

0

1

0

0

A0

X R/W

X = Don’t care.

START

CONDITION

1

SCL

CLOCK PULSE FOR ACKNOWLEDGE

2

8

9

SDA BY

TRANSMITTER

S

SDA BY

RECEIVER

Figure 9. Acknowledge

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