HN58X25128TI データシートの表示（PDF） - Renesas Electronics

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HN58X25128TI

Serial Peripheral Interface 128k EEPROM (16-kword × 8-bit) 256k EEPROM (32-kword × 8-bit) Electrically Erasable and Programmable Read Only Memory

Renesas Electronics 

HN58X25128I/HN58X25256I

Functional Description Functional Description

Status Register

The following figure shows the Status Register Format. The Status Register contains a number of status and

control bits that can be read or set (as appropriate) by specific instructions.

Status Register Format

b7

b0

SRWD 0

0

0

BP1 BP0 WEL WIP

Status Register Write Disable

Block Protect Bits

Write Enable Latch Bits

Write In Progress Bits

WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status

Register cycle.

WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Write instructions.

SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect

(W) signal. The Status Register Write Disable (SRWD) bit and write protect (W) signal allow the device to

be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD,

BP1, BP0) become read-only bits.

Instructions

Each instruction starts with a single-byte code, as summarized in the following table . If an invalid

instruction is sent (one not contained in the following table), the device automatically deselects itself.

Rev.1.00, Jun.20.2003, page 13 of 27

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