TN28F010-150 データシートの表示（PDF） - Intel

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TN28F010-150

28F010 1024K (128K X 8) CMOS FLASH MEMORY

Intel 

E

28F010

Start

Programming (4)

Apply VPPH (1)

Bus

Operation

Command

Comments

Standby

Wait for VPP Ramp to

VPPH(1)

PLSCNT = 0

Initialize Pulse-Count

Increment

Address

Write Set-Up

Program Cmd

Write Program

Cmd (A/D)

Time Out 10 µs

Write Program

Verify Cmd

Time Out 6 µs

Read Data

from Device

Verify

N

Data

Y

N

Last

Address?

Y

Write Read Cmd

N

Inc

PLSCNT

=25?

Y

Write

Write

Set-Up

Program

Data = 40H

Program Valid Address/Data

Standby

Write

Duration of Program

Operation (tWHWH1 )

Program

Verify(2)

Data = C0H; Stops

Program Operations(3)

Stand-by

Read

tWHGL

Read Byte to Verify

Programming

Standby

Compare Data Output to

Data Expected

Write

Read

Data = 00H, Resets the

Register for Read

Operations

Standby

Wait for VPP Ramp to VPPL(1)

Apply VPPL (1)

Apply VPPL (1)

Programming

Completed

Program

Error

0207_04

NOTES:

1. See DC Characteristics for the value of VPPH and VPPL.

2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the

register is written with the Read command.

3. Refer to Principles of Operation.

4. CAUTION: The algorithm must be followed to ensure proper and reliable operation of the device.

Figure 4. 28F010 Quick-Pulse Programming Algorithm

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