CY7C1464AV25(2004) データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
メーカー
CY7C1464AV25
(Rev.:2004)
(Rev.:2004)
Cypress Semiconductor
CY7C1464AV25 Datasheet PDF : 27 Pages
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PRELIMINARY
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Function (CY7C1462AV25)
Read
Write – No Bytes Written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
Function (CY7C1464AV25)
Read
Write – No Bytes Written
Write Byte X − (DQx and DQPx)
Write All Bytes
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 incor-
porates a serial boundary scan test access port (TAP). This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 2.5V/1.8V I/O logic level.
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 contains
a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
TAP Controller State Diagram
1 TEST-LOGIC
RESET
0
0 RUN-TEST/ 1
IDLE
SELECT
1
DR-SCAN
0
1
CAPTURE-DR
0
SHIFT-DR 0
1
1
EXIT1-DR
0
PAUSE-DR 0
1
0
EXIT2-DR
1
UPDATE-DR
10
SELECT
1
IR-SCAN
0
1
CAPTURE-IR
0
SHIFT-IR
0
1
1
EXIT1-IR
0
PAUSE-IR 0
1
0
EXIT2-IR
1
UPDATE-IR
10
WE
BWb
H
x
L
H
L
H
L
L
L
L
WE
H
L
L
L
BWa
x
H
L
H
L
BWx
x
H
L
All BW = L
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Document #: 38-05354 Rev. *A
Page 10 of 27
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