CY7C1464AV25(2004) データシートの表示（PDF） - Cypress Semiconductor

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CY7C1464AV25
(Rev.:2004)

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Pin Definitions (continued)

Pin Name

I/O Type

Pin Description

BWa

BWb

BWc

BWd

BWe

BWf

BWg

BWh

WE

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,

BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf

controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.

Input-

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

Synchronous signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

Synchronous

Advance/Load Input used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a

new address can be loaded into the device for an access. After being deselected, ADV/LD should

be driven LOW in order to load a new address.

ADV/LD

Input-

Synchronous

Advance/Load Input used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a

new address can be loaded into the device for an access. After being deselected, ADV/LD should

be driven LOW in order to load a new address.

CLK

Input-

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

Clock

CLK is only recognized if CEN is active LOW.

CE1

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

Synchronous CE2 and CE3 to select/deselect the device.

CE2

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

Synchronous CE1 and CE3 to select/deselect the device.

CE3

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

Synchronous CE1 and CE2 to select/deselect the device.

OE

Input-

Output Enable, active LOW. Combined with the synchronous logic block inside the device to

Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.

When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during

the data portion of a write sequence, during the first clock when emerging from a deselected state

and when the device has been deselected.

CEN

Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the

SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not

deselect the device, CEN can be used to extend the previous cycle when required.

DQa

DQb

DQc

DQd

DQe

DQf

DQg

DQh

DQPa

DQPb

DQPc

DQPd

DQPe

DQPf

DQPg

DQPh

MODE

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by AX during the previous clock rise of the read cycle. The direction of the pins is

controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave

as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automat-

ically tri-stated during the data portion of a write sequence, during the first clock when emerging

from a deselected state, and when the device is deselected, regardless of the state of OE.

I/O-

Synchronous

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During

write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by

BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf,

DQPg is controlled by BWg, DQPh is controlled by BWh.

Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

Pulled LOW selects the linear burst order. MODE should not change states during operation.

When left floating MODE will default HIGH, to an interleaved burst order.

TDO

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

Synchronous

TDI

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

Synchronous

Document #: 38-05354 Rev. *A

Page 6 of 27

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