CY7C1464AV25(2004) データシートの表示（PDF） - Cypress Semiconductor

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CY7C1464AV25
(Rev.:2004)

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Pin Definitions (continued)

Pin Name

I/O Type

Pin Description

TMS

Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

Synchronous

TCK

JTAG-Clock Clock input to the JTAG circuitry.

VDD

VDDQ

VSS

NC

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

Ground

Ground for the device. Should be connected to ground of the system.

N/A

No connects. This pin is not connected to the die.

NC/72M

N/A

Not connected to the die. Can be tied to any voltage level.

NC/144M

N/A

Not connected to the die. Can be tied to any voltage level.

NC/288M

N/A

Not connected to the die. Can be tied to any voltage level.

ZZ

Input-

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

Asynchronous with data integrity preserved. During normal operation, this pin can be connected to Vss or left

floating.

Introduction

Functional Overview

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are

synchronous-pipelined Burst NoBL SRAMs designed specifi-

cally to eliminate wait states during Write/Read transitions. All

synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock signal is qualified with

the Clock Enable input signal (CEN). If CEN is HIGH, the clock

signal is not recognized and all internal states are maintained.

All synchronous operations are qualified with CEN. All data

outputs pass through output registers controlled by the rising

edge of the clock. Maximum access delay from the clock rise

(tCO) is 2.6 ns (250-MHz device).

Accesses can be initiated by asserting all three Chip Enables

(CE1, CE2, CE3) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a read or write operation, depending on

the status of the Write Enable (WE). BW[x] can be used to

conduct byte write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory core

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the input of the output register. At the rising edge

of the next clock the requested data is allowed to propagate

through the output register and onto the data bus within 2.6 ns

(200-MHz device) provided OE is active LOW. After the first

clock of the read access the output buffers are controlled by

OE and the internal control logic. OE must be driven LOW in

order for the device to drive out the requested data. During the

second clock, a subsequent operation (Read/Write/Deselect)

can be initiated. Deselecting the device is also pipelined.

Therefore, when the SRAM is deselected at clock rise by one

of the chip enable signals, its output will three-state following

the next clock rise.

Burst Read Accesses

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 have

an on-chip burst counter that allows the user the ability to

supply a single address and conduct up to four Reads without

reasserting the address inputs. ADV/LD must be driven LOW

in order to load a new address into the SRAM, as described in

the Single Read Access section above. The sequence of the

burst counter is determined by the MODE input signal. A LOW

input on MODE selects a linear burst mode, a HIGH selects an

interleaved burst sequence. Both burst counters use A0 and

A1 in the burst sequence, and will wrap-around when incre-

mented sufficiently. A HIGH input on ADV/LD will increment

the internal burst counter regardless of the state of chip

enables inputs or WE. WE is latched at the beginning of a burst

cycle. Therefore, the type of access (Read or Write) is

maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are ALL asserted active, and (3) the write signal WE

is asserted LOW. The address presented to the address inputs

is loaded into the Address Register. The write signals are

latched into the Control Logic block.

On the subsequent clock rise the data lines are automatically

three-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h

for

CY7C1464AV25,

DQa,b,c,d/DQPa,b,c,d for CY7C1460AV25 and DQa,b/DQPa,b

for CY7C1462AV25). In addition, the address for the subse-

quent access (Read/Write/Deselect) is latched into the

Address Register (provided the appropriate control signals are

asserted).

On the next clock rise the data presented to DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h

for

CY7C1464AV25,

DQa,b,c,d/DQPa,b,c,d for CY7C1460AV25 and DQa,b/DQPa,b

for CY7C1462AV25) (or a subset for byte write operations, see

Document #: 38-05354 Rev. *A

Page 7 of 27

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