CY7C1464AV25(2004) データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
メーカー
CY7C1464AV25
(Rev.:2004)
(Rev.:2004)
Cypress Semiconductor
CY7C1464AV25 Datasheet PDF : 27 Pages
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PRELIMINARY
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Truth Table[1, 2, 3, 4, 5, 6, 7]
Operation
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/WRITE ABORT (Begin Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
Sleep MODE
Address
Used CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
None
HL
L
X
X
X L L-H Three-State
None
XL
H
X
X
X L L-H Three-State
External L L
L
H
X
L L L-H Data Out (Q)
Next
XL
H
X
X
L L L-H Data Out (Q)
External
L
L
L
H
X
H L L-H Three-State
Next
XL
H
X
X
H L L-H Three-State
External L L
L
L
L
X L L-H Data In (D)
Next
XL
H
X
L
X L L-H Data In (D)
None
LL
L
L
H
X L L-H Three-State
Next
XL
H
X
H
X L L-H Three-State
Current
XL
X
X
X
X H L-H
–
None
XH
X
X
X
X X X Three-State
Partial Write Cycle Description[1, 2, 3, 8]
Read
Function (CY7C1460AV25)
WE
BWd
BWc
BWb
BWa
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Bytes b, a
L
H
H
H
L
L
H
H
L
H
L
H
H
L
L
Write Byte c – (DQc and DQPc)
Write Bytes c, a
L
H
L
H
H
L
H
L
H
L
Write Bytes c, b
L
H
LL
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
Write Bytes d, a
L
L
H
H
H
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWX. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Three-state when
OE is inactive or when the device is deselected, and DQs=data when OE is active.
8. Table only lists a partial listing of the byte write combinations. Any combinaion of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05354 Rev. *A
Page 9 of 27
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