M1502 データシートの表示（PDF） - Motorola => Freescale
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M1502 Datasheet PDF : 7 Pages
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Table 1. Port Impedance Derived from Circuit Characterization
Pin Number
44
40
39
32
Pin Name
RF IN
TO BPF
FROM BPF
IF OUT
f
(MHz)
1575.42
47.74
47.74
9.5
Zin
Ohms
R
jX
38.3
–16.09
54.45
11.3
43
1.5
560
–850
Zin represents the input impedance of the pin.
APPLICATION INFORMATION
Design Philosophy
The MRFIC1502 design is a standard dual downconver-
sion configuration with an integrated fixed frequency phase–
locked loop to generate the two local oscillators and the
buffer to generate the sampling clock for a digital correlator
and decimator. The active device for the L–band VCO is also
integrated on the chip. This chip is designed in the third
generation of Motorola’s Oxide Self Aligned Integrated
Circuits (MOSAIC 3) silicon bipolar process.
Circuit Considerations
The RF input to the MRFIC1502 is internally matched to 50
ohms. Therefore, only AC coupling is required on the input.
The output of the amplifier is fed directly into the first mixer.
This mixer is an active Gilbert Cell configuration. The output
of the mixer is brought off–chip for filtering of the unwanted
mixer products. The amplifier and mixer have their own VCC
supply (pin 42) in order to reduce the amount of coupling to
the other circuits. There are two bypass capacitors on this
pin, one for the high frequency components and one for the
lower frequency components. These two capacitors should
be placed physically as close to the bias pin as possible to
reduce the inductance in the path. The capacitors should
also be grounded as close to the ground of the IC as
possible, preferably through a ground plane.
The output impedance of the first mixer is 50 ohms, while
the input impedance to the first IF amplifier is 1 kΩ. There is
a trap (zero) designed in at the second LO frequency to limit
the amount of LO leakage into the high gain first IF amplifier.
The first IF amplifier is a variable gain amplifier with 25 dB
of gain and 40 dB of gain control. The gain control pin can be
grounded to provide the maximum gain out of the amplifier. If
the baseband design utilizes a multi–bit A/D converter in the
digital signal processing chip, this amplifier could be used to
control the input to the A/D converter. The amplifier has an
external bypassing capacitor. This capacitor should be on the
order of 0.01 µF, and again should be located near the
package pin.
The second mixer design is also a Gilbert Cell configura-
tion. The interface between the mixer and the second IF
amplifier is differential in order to increase noise immunity.
This differential interface is also brought off–chip so that
some additional filtering could be added in parallel between
the output of the mixer and input to the amplifier. This filtering
is primarily to reduce the amount of LO leakage into the final
IF amplifier and is achieved using a single 3.9 pF capacitor
across the differential ports. The value of the capacitor
determines the high frequency of the low pass structure.
The supply pin for the IF circuits is pin 33. This supply pin
should be isolated from the other chip supplies in order to
reduce the amount of coupling. The recommended capaci-
tors are a 47 pF and a 0.01 µF, in parallel to bypass the
supply to ground and should be placed physically as close to
the pin as possible.
The output of the second IF amplifier is 50 ohms with a
bandwidth of ±5.0 MHz. This signal must be filtered before
being digitized in order to limit the noise entering the A/D
converter.
VCO Resonator Design
The design and layout of the circuits around the voltage
controlled oscillator (VCO) are the most sensitive of the
entire layout. The active device and biasing resistors are
integrated on the MRFIC1502. The external circuits consist
of the power supply decoupling, the capacitors for the
integrated supply superfilter, the resonator and frequency
adjusting elements, and the bypassing capacitor on the
emitter of the active device.
The VCO supply is isolated from the rest of the PLL circuits
in order to reduce the amount of noise that could cause
frequency/phase noise in the VCO. The supply should be
filtered using a 22 µH inductor in series and a 27 pF and
0.01 µF in parallel. The 27 pF capacitor should be series
resonant at least as high as the VCO frequency to get the
most L–band bypassing as possible. The on–chip supply
filter requires two capacitors off–chip to filter the supply. The
capacitors on the input (pin 8) and output (pin 10) of the filter
are 1.0 µF, and the output also has a high frequency bypass
capacitor in parallel. The input capacitor should not be smaller
than a 1.0 µF to insure stability of the supply filter.
The VCO design is a standard negative resistance cell with
a buffer amplifier. The resonating structure is connected to
the base of the active device and consists of a coupling
capacitor, a hyper–abrupt varactor diode, and a wire wound
chip inductor. With the values shown on the application
MRFIC1502
4
MOTOROLA RF DEVICE DATA
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