Horizontal Direction Input Signal Timing Chart
310
315
320
MCK
Hsync∗1
DENB∗1
DATA 307 308 309 310 311 312 313 314 315 316 317 318 319 320
325
330
16 dots
MCK
thss
Hsync∗1
DENB∗1
DATA
thsw
∗1 Input either Hsync + Vsync or DENB as sync input signal.
tdes
1
tds tdh
335
340
345
350 0
352 dots
5
4 dots (min.)
32 dots
16 dots
1 2 3 4 5 6 7 8 9 10 11
tch tcl
tclk
tdeh
2
320
Input Signal AC Characteristics (VDD1 = 3.0 to 3.6V, Ta = –25 to +75°C)
Item
Symbol Min.
Typ.
Max.
MCK frequency
MCK low, high pulse width
DATA setup time
DATA hold time
DENB setup time
DENB hold time
Hsync setup time
Hsync low pulse width
ftch
tch, tcl
tds
tdh
tdes
tdeh
thss
thsw
3MHz
—
10ns
15ns
10ns
15ns
10ns
4tclk
5.58MHz
0.5tclk
—
—
—
—
—
—
8MHz
—
—
—
—
—
—
16tclk