T8301 データシートの表示（PDF） - Agere -> LSI Corporation

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T8301

Internet Protocol Telephone Phone-On-A-Chip™ IP Solution DSP

Agere -> LSI Corporation 

Advance Data Sheet

December 2000

T8301 Internet Protocol Telephone

Phone-On-A-Chip IP Solution DSP

5 Audio Input/Output Circuitry (continued)

5.6 Audio Codec Control Registers

The analog audio input and output control register (aioc_reg) is used to select the active and enabled inputs

and outputs. Through this register the input and output channels can also have the clocks shut down to conserve

power.

Table 11. aioc_reg Analog Audio I/O Control

Bit #

Name

Bit #

Name

Analog Audio Input and Output Control Register (aioc_reg): Address (0x4000)

15

14

13

12

11

10

MPWRD

SPKFB

HNDFB

AINFB

SPK2EN

OLE

7

6

5

4

3

2

RSVD

PGAS(2) PGAS(1) PGAS (0)

SPKEN AOUTAEN

9:8

RSVD

1:0

AINSS[1:0]

Bit #

15

14

Name

MPWRD

SPKFB

Value

at Reset

1

0*

Description

Main powerdown.

If 1, powerdown.

If 0, powerup.

Speaker #1 output filter bypass.

If 1, the transmit LPF is bypassed in the speaker path; set the correspond-

ing DMA clock to 16 kHz.

If 0, the transmit LPF is enabled in the speaker path.

Note: The SOC bits in the audio codec clock control register should

also be modified.

13

HNDFB

0* Handset output filter bypass.

If 1, the transmit LPF is bypassed in the handset path; set the correspond-

ing DMA clock to 16 kHz.

If 0, the transmit LPF is enabled in the handset path.

Note: The HOC bits in the audio codec clock control register should

also be modified.

12

AINFB

0* Analog input filter bypass.

If 1, the receive BPF is bypassed in the audio input path; set the corre-

sponding DMA clock to 16 kHz.

If 0, the receive BPF is enabled in the audio input path.

Note: The AINC bits in the audio codec clock control register should

also be modified.

11

SPK2EN

0

Enables speaker #2 output channel.

If 1, the speaker’s output driver is enabled.

If 0, the output driver for the speaker output channel is disabled.

10

OLE

0

Output limit enable. When set, this bit causes the nominal full-scale output

for the analog outputs to be limited to approximately half the normal value

of 2.5 Vp-p Setting this bit has no effect on the receive gain.

9:7

RSVD

Reserved.

* If the BPF is bypassed, output from the decimator must be shifted right by 2 bits (6 dB attenuation) to avoid saturation going into the com-

pander. Similarly, if the LPF is bypassed in the speaker or handset path, input into the interpolator must be shifted left by 2 bits.

Lucent Technologies Inc.

21

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