HEF40174B データシートの表示（PDF） - NXP Semiconductors.
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HEF40174B Datasheet PDF : 14 Pages
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NXP Semiconductors
HEF40174B
Hex D-type flip-flop
Table 7. Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; or test circuit see Figure 5; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Extrapolation formula
th
hold time
Dn to CP;
see Figure 4
5V
10 V
15 V
tW
pulse width
CP input LOW;
minimum width;
see Figure 4
5V
10 V
15 V
MR input LOW;
minimum width;
see Figure 4
5V
10 V
15 V
trec
recovery time
MR input;
see Figure 4
5V
10 V
15 V
fmax
maximum frequency see Figure 4
5V
10 V
15 V
[1] tt is the same as tTHL and tTLH.
Min Typ Max Unit
10 0
-
ns
5
0
-
ns
5
0
-
ns
70 35 -
ns
30 15 -
ns
20 10 -
ns
70 35 -
ns
35 15 -
ns
25 10 -
ns
45 25 -
ns
20 10 -
ns
15 5
-
ns
5
11 -
MHz
15 30 -
MHz
20 45 -
MHz
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD
Typical formula for PD (W)
where:
PD
dynamic power 5 V
PD = 3500 fi + (fo CL) VDD2
fi = input frequency in MHz,
dissipation
10 V
PD = 16000 fi + (fo CL) VDD2
fo = output frequency in MHz,
15 V
PD = 42000 fi + (fo CL) VDD2
CL = output load capacitance in pF,
VDD = supply voltage in V,
(fo CL) = sum of the outputs.
HEF40174B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
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