AD9940 データシートの表示（PDF） - Analog Devices
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AD9940 Datasheet PDF : 20 Pages
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AD9940
SERIAL INTERFACE TIMING
All the internal registers of the AD9940 are accessed through
a 3-wire serial interface. Each register consists of an 8-bit data
byte starting with the LSB bit. As shown in Figure 5, the data
bits are clocked in on the rising edge of SCK after SL is asserted
low and the entire 8-bit word is latched in on the rising edge
of SL after the last MSB bit. Consecutive serial writes are per-
formed starting with Address 0 and ending with an address
MSB bit prior to asserting SL high.
The AD9940 contains two banks of registers, which are
programmed independently. Bank 1 consists of the registers
located at Address 0 to Address 13, and Bank 2 consists of
Address 14 to Address 26. The WRITEMODE register located
at Address 0 is used to select which register bank is written to.
Data Sheet
Every write operation must begin with a write to Address 0 to
specify Part select bit and Bank location, then followed with any
number of consecutive data words. Address 0 is always followed
by Address 01 or Address 14 depending on the value specified
for WRITEMODE (used for Bank selection).
A hard reset is recommended after power-up to reset the
AD9940 prior to performing a serial interface write. A hard
reset is performed by asserting the RST pin low for a mini-
mum of 10 μs. The serial interface pins SCK, SL, and SDI
must be in a know state after the RST has been applied.
ADDR 00
ADDR 01
ADDR N
ADDR N+1
SDATA
tDS
SCK
D0 D1 D2 D3 ... D7 D0 D1 D2 D3 ... D7 D0 D1 D2 D3 ... D7 D0 D1 D2 D3 ... D7
tDH
...
...
...
...
tLS
tLH
SL
...
NOTES
1. ANY NUMBER OF ADJACENT REGISTERS CAN BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS 00.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED
FOR EACH REGISTER.
3. ALL LOADED REGISTERS ARE SIMULTANEOUSLY UPDATED ON THE RISING EDGE OF SL.
Figure 5. Serial Interface Operation
Rev. A | Page 12 of 20
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