AD9940 データシートの表示（PDF） - Analog Devices

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AD9940

High Speed, Correlated Double Sampler with Integrated Timing Driver

Analog Devices 

Data Sheet

AD9940

SYSTEM OVERVIEW

Figure 6 shows the typical system block diagram for the

AD9940. The CCD output is processed by the AD9940’s

AFE circuitry, which consists of a correlated double sam-

pler (CDS) and output buffer. The differential output of the

AD9940 provides good signal integrity when interfaced with

the AD9941.

To operate the AD9940, all CCD and AFE timing parameters

are programmed into the AD9940 from the system micro-

processor through the 3-wire serial interface. From the system

master clock, CLI, provided by the image processor or external

crystal, the AD9940 generates the CCD’s horizontal and reset

gate clocks and all internal AFE clocks.

The H-drivers for H1 to H4, HL and RG, are included in the

AD9940, allowing these clocks to be directly connected to the

CCD. An H-drive voltage of up to 3.6 V is supported.

ANALOG FRONT END OPERATION

The AD9940 signal-processing chain is shown in Figure 7,

consisting of a dc restore circuit, CDS, and output buffer.

DC Restore

To reduce the large dc offset of the CCD output signal, a

dc restore circuit is used with an external 0.1 μF series

coupling capacitor. This restores the dc level of the CCD

signal to approximately 1.5 V to be compatible with the 3 V

analog supply of the AD9940.

Correlated Double Sampler

The CDS circuit samples each CCD pixel twice to extract

the video information and reject low frequency noise. The

timing diagram in Figure 10 illustrates how the two internally

generated CDS clocks, SHP and SHD, are used to sample the

reference level and the data level, respectively, of the CCD

signal. The placement of the SHP and SHD sampling edges

is determined by the setting of the SHPLOC (Address 22)

and SHDLOC (Address 23) control registers. Placement of

these two clock edges is critical to achieve the best perform-

ance from the CCD.

CCD

VOUT

AD9940

DIFFN

0.1F

BUFOUT DIFFP

CCDIN

CIN

BUFFER

H1–H4, HL, RG

REGISTER

DATA

TIMING

GENERATOR

AD9941 DIGITAL

OUTPUTS DIGITAL IMAGE

ADCOUT

PROCESSING

ASIC

REGISTER

DATA

SERIAL

INTERFACE

Figure 6. Typical System Block Diagram

DC RESTORE

+

1.5V

AD9940

SHP

0.1F

REFB

1V

0.1F

REFT

2V

INTERNAL

VREF

CCDIN

0.1F

CDS

SHD

SHP SHD

BUF

DIFFN

DIFFP

H1–H4, HL, RG

TIMING

GENERATION

PRECISION

TIMING

GENERATION

SERIAL INTERFACE

Figure 7. AD9940 Signal-Processing Chain

Rev. A | Page 13 of 20

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