AD9940 データシートの表示（PDF） - Analog Devices

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AD9940

High Speed, Correlated Double Sampler with Integrated Timing Driver

Analog Devices 

AD9940

Data Sheet

PRECISION TIMING, HIGH SPEED TIMING GENERATION

The AD9940 generates flexible, high speed timing signals

using the Precision Timing core. This core is the foundation for

generating the timing used for both the CCD and the AFE: the

reset gate RG, horizontal drivers H1 to H4, and the SHP/SHD

sample clocks. A unique architecture makes it routine for the

system designer to optimize image quality by providing precise

control over the horizontal CCD readout and the AFE corre-

lated double sampling.

TIMING RESOLUTION

The Precision Timing core uses a 1× master clock input (CLI)

as a reference. This clock should be the same as the CCD pixel

clock frequency. Figure 8 illustrates how the internal timing

core divides the master clock period into 48 steps or edge

positions. Therefore, the edge resolution of the Precision

Timing core is (tCLI/48).

HIGH SPEED CLOCK PROGRAMMABILITY

Figure 9 shows how the high speed clocks, RG, HL, H1–H4, SHP,

and SHD are generated. The RG pulse has programmable rising

and falling edges, and can be inverted using the polarity control.

The horizontal clocks H1/H3 have programmable rising and

falling edges, and polarity control. The H2/H4 clocks are always

inverses of the H1/H3 H-driver outputs.

Table 8 summarizes the high speed timing registers and their

parameters. Each edge location setting is 6 bits wide, but only

48 valid edge locations are available. Therefore, the register

values are mapped into four quadrants, with each quadrant

containing 12 edge locations. Table 9 shows the correct reg-

ister values for the corresponding edge locations.

POSITION

P[0]

CLI

tCLIDLY

1 PIXEL

PERIOD

P[12]

...

P[24]

P[36]

P[48] = P[0]

...

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6 ns TYP).

Figure 8. High Speed Clock Resolution from CLI Master Clock Input

Rev. A | Page 14 of 20

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