AD9940 データシートの表示（PDF） - Analog Devices
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AD9940 Datasheet PDF : 20 Pages
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Data Sheet
APPLICATIONS INFORMATION
All signals should be carefully routed on the PCB to main-
tain low noise performance. The CCD output signal should be
connected to the CCDIN pin through a 0.1 µF capacitor. The
CCD timing signals H1A/B to H2A/B and RG1 to RG2 should
be routed directly to the CCD with minimum trace lengths. The
clock inputs are located on the other side of the package, where
the analog pins are located, and should be connected to the
digital ASIC away from the analog and CCD clock signals.
A single ground plane is recommended for the AD9940. This
ground plane should be as continuous as possible, particularly
where analog pins are concentrated, to ensure that all analog
decoupling capacitors provide the lowest possible impedance
path between the power and bypass pins and their respective
ground pins.
AD9940
All decoupling capacitors should be located as close as possible
to the package pins. Careful use of a split ground plane can be
effective to avoid the return current of horizontal driver flows
into analog ground, thereby reducing coupling noise.
Power-supply decoupling is very important for achieving low
noise performance. Figure 15 shows the local high frequency
decoupling capacitors, but additional capacitance is recom-
mended for lower frequencies. Additional capacitors and
ferrite beads can further reduce noise.
When using the LFCSP package, it is recommended that the
exposed paddle on the bottom of the package be soldered
to a large pad, with multiple vias connecting the pad to the
ground plane.
0.1µF
0.1µF
0.1µF
3V ANALOG SUPPY
3V ANALOG SUPPLY
0.1µF
DIFFN OUTPUT
DIFFP OUTPUT
3V ANALOG SUPPLY
0.1µF
3V ANALOG SUPPLY
MASTER 0.1µF
CLOCK INPUT
3V ANALOG SUPPLY 4.7µF+ 0.1µF
NC
1
AVSS
2
AVDD
3
DIFFN
4
DIFFP
5
OVSS
6
OVDD
7
TCVDD
8
CLI
9
TCVSS
10
DVSS 11
DVDD 12
48 47 46 45 44 43 42 41 40 39 38 37
PIN 1
AD9940
TOP VIEW
(Not to Scale)
AVSS
36
CCDIN
35
AVSS
34
SHP
33
SHD
32
AVSS
31
H1
30
H2
29
HVSS
28
HVDD
27
H3
26
H4
25
13 14 15 16 17 18 19 20 21 22 23 24
ANALOG OUTPUT
FROM CCD
2
CCD SAMPLING INPUTS
0.1µF
4.7µF+
4
3V ANALOG
SUPPLY
HORIZONTAL
CLOCKS TO CCD
SERIAL
INTERFACE
RST INPUT
HD INPUT
RG
HL
3
3V ANALOG SUPPLY
0.1µF
Figure 15. Recommended Circuit Configuration
Rev. A | Page 19 of 20
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