AD7883 データシートの表示（PDF） - Analog Devices
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AD7883 Datasheet PDF : 12 Pages
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AD7883
CIRCUIT INFORMATION
The AD7883 is a single supply 12-bit A/D converter. The part
requires no external components apart from a 2 MHz external
clock and power supply decoupling capacitors. It contains a
12-bit successive approximation ADC based on a fast-settling
voltage output DAC, a high speed comparator and SAR, as well
as the necessary control logic. The charge balancing comparator
used in the AD7883 provides the user with an inherent track-
and-hold function. The ADC is specified to work with sampling
rates up to 50 kHz.
CONVERTER DETAILS
The AD7883 conversion cycle is initiated on the rising edge of
the CONVST pulse, as shown in the timing diagram of Figure
1. The rising edge of the CONVST pulse places the track/hold
amplifier into “HOLD” mode. The conversion cycle then takes
between 26 and 28 clock periods. The maximum specified con-
version time is 15 µs. During conversion the BUSY output will
remain low, and the output databus drivers will be three-stated.
When a conversion is completed, the BUSY output will go to a
high level, and the result of the conversion can be read by bring-
ing CS and RD low.
The track/hold amplifier acquires a 12-bit input signal in 5 µs.
The overall throughput time for the AD7883 is equal to the con-
version time plus the track/hold acquisition time. For a 2 MHz
input clock the throughput time is 20 µs.
The AD7883 accommodates two separate input ranges, 0 to
VREF and ± VREF. The input configurations corresponding to
these ranges are shown in Figures 4 and 5.
With VREF = VDD and using a nominal VDD of +3.3 V, the input
ranges are 0 V to 3.3 V and ± 3.3 V, as shown in Table II.
Table II. Analog Input Ranges
Analog Input
Range
0 V to +3.3 V
± 3.3 V
VREF
VDD
VDD
Input Connections
VINA
VINB
VIN
VIN
VIN
VREF
Connection
Diagram
Figure 4
Figure 5
VIN = 0 TO VREF
VREF
R
VINA
R
VINB
VREF
AGND
SAMPLING
COMPARATOR
0 TO VREF
+
–
12-BIT DAC
Figure 4. 0 to VREF Unipolar Input Configuration
REFERENCE INPUT
For specified performance, it is recommended that the reference
input be tied to VDD. The part, however, will operate with a
reference down to 2.5 V though with reduced performance
specifications.
VREF must not be allowed to go above VDD by more than 100 mV.
ANALOG INPUT
The AD7883 has two analog input pins, VINA and VINB. Figure
3 shows the input circuitry to the ADC sampling comparator.
The onboard attenuator network, made up of equal resistors, al-
lows for various input ranges.
R
VINA
+
R
VINB
–
VIN = ±VREF
VREF
R
VINA
R
VINB
VREF
AGND
SAMPLING
COMPARATOR
0 TO VREF
+
–
12-BIT DAC
Figure 5. ±VREF Bipolar Input Configuration
VDAC
Figure 3. AD7883 Input Circuit
REV. 0
–5–
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