KSZ9021RLI データシートの表示（PDF） - Micrel

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KSZ9021RLI

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9021RL/RN

Pin Number

32

33

34

35

36

Pin Name

RXD0 /

MODE0

RX_DV /

CLK125_EN

DVDDH

RX_CLK /

PHYAD2

MDC

37

MDIO

38

INT_N

39

DVDDL

40

DVDDH

41

CLK125_NDO /

LED_MODE

42

RESET_N

43

LDO_O

44

45

46

47

48

PADDLE

AVDDL_PLL

XO

XI

AVDDH

ISET

P_GND

Type(1)

I/O

I/O

P

I/O

Ipu

Ipu/O

O

P

P

I/O

Ipu

O

P

O

I

P

I/O

Gnd

Pin Function

RGMII Mode: RGMII RD0 (Receive Data 0) Output /

Config Mode: The pull-up/pull-down value is latched as MODE0 during

power-up/reset. See “Strapping Options” section for details.

RGMII Mode: RGMII RX_CTL (Receive Control) Output /

Config Mode: Latched as CLK125_NDO Output Enable during power-up/

reset. See “Strapping Options” section for details.

3.3V/2.5V digital VDD

RGMII Mode: RGMII RXC (Receive Reference Clock) Output /

Config Mode: The pull-up/pull-down value is latched as PHYAD[2] during

power-up/reset. See “Strapping Options” section for details.

Management Data Clock Input

This pin is the input reference clock for MDIO (pin 37).

Management Data Input/Output

This pin is synchronous to MDC (pin 36) and requires an external pull-up resistor

to 3.3V/2.5V digital VDD in a range from 1.0kΩ to 4.7kΩ.

Interrupt Output

This pin provides a programmable interrupt output and requires an external pull-up

resistor to 3.3V/2.5V digital VDD in a range from 1.0kΩ to 4.7kΩ when active low.

Register 1Bh is the Interrupt Control/Status Register for programming the interrupt

conditions and reading the interrupt status. Register 1Fh bit 14 sets the interrupt

output to active low (default) or active high.

1.2V digital VDD

3.3V/2.5V digital VDD

125MHz Clock Output

This pin provides a 125MHz reference clock output option for use by the MAC. /

Config Mode: The pull-up/pull-down value is latched as LED_MODE during

power-up/reset. See “Strapping Options” section for details.

Chip Reset (active low)

Hardware pin configurations are strapped-in at the de-assertion (rising edge) of

RESET_N. See “Strapping Options” section for more details.

On-chip 1.2V LDO Controller Output

This pin drives the input gate of a P-channel MOSFET to generate 1.2V for the

chip’s core voltages. If 1.2V is provided by the system and this pin is not used, it

can be left floating.

1.2V analog VDD for PLL

25MHz Crystal feedback

This pin is a no connect if oscillator or external clock source is used.

Crystal / Oscillator / External Clock Input

25MHz ±50ppm tolerance

3.3V analog VDD

Set transmit output level

Connect a 4.99kΩ 1% resistor to ground on this pin.

Exposed Paddle on bottom of chip

Connect P_GND to ground.

February 13, 2014

19

Revision 1.2

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