UBA20262 データシートの表示（PDF） - NXP Semiconductors.
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UBA20262 Datasheet PDF : 32 Pages
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NXP Semiconductors
UBA20261/2
600 V and 350 V power IC for step dimmable CFLs
BOOST AND BURN
STATES
00
burn select
Temp < Tj(bp)bst AND
NOT Boost_Disable
boost timer running
01
boost
Dim_1 state AND Boost
Boost_ratio = 1
Boost_ratio = 1.5
NOT (Boost OR Boost transition)
Temp > Tj(bp)(bst) OR
Boost_Disable
Temp < Tj(otp) - Tj(otp)(hys)
Vi(CSI) = Votp(CSI)
(66 % level)
Vi(CSI) = Vdamp(CSI)
(100 % level)
Temp > Tj(otp)
Temp > Tj(end)bst
OR boost timer ended
10
burn
boost_transition timer ended
OR temp > Tj(otp)
Fig 7. Boost and burn state machine
11
boost transition
001aam767
7.1.7 Hold state
The hold state is a special state that reduces lamp flicker at deep dim levels, on or near
dim and ignition threshold levels. The IC enters the hold state after an ignition failure or
when the low supply voltage VDD drops below VDD(stop) in the ignition or preheat states
(see Figure 3).
A repeated drop in supply voltage below VDD(stop) in preheat or ignition states, does not
increment the ignition attempt counter. The hold state is entered, delaying a new preheat
cycle with the same time delay/mechanism by the hold state retention time as shown in
Figure 5.
When CP is below Vth(rel)CP, the IC is released from the hold state and moves to the
start-up state as shown in Figure 3. Alternatively, the hold state ends when the supply
voltage drops below VDD(rst) and the IC is reset.
With a 470 nF capacitor on the CP pin, the typical hold state retention delay is between
1 s and 1.7 s. This delay is dependent on where the preheat cycle was cut-off on the rising
or falling edge of the preheat timing. The retention time for a failed ignition always starts
from the top of the rising edge on the CP pin (see Figure 5).
In the hold state, a hold state latch is set (hold state latch = 1) and the oscillator is
stopped. In addition, the HS transistor is non-conductive and the LS transistor is
conducting.
The voltage on the VDD pin alternates between VDD(start) and VDD(stop) until the voltage on
the CP pin reaches Vth(rel)CP (see Figure 5). The alternating supply voltage is caused by
the current drawn by the IC supply pin VDD. The supply current is less than 220 A, when
UBA20261_UBA20262
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 October 2011
© NXP B.V. 2011. All rights reserved.
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