UBA20262 データシートの表示（PDF） - NXP Semiconductors.

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UBA20262

600 V and 350 V power IC for step dimmable CFLs

NXP Semiconductors. 

NXP Semiconductors

UBA20261/2

600 V and 350 V power IC for step dimmable CFLs

the supply voltage VDD rises between VDD(stop) and VDD(start). Typically, the supply current

is 2 mA when VDD falls between VDD(start) and VDD(stop). More current is drawn during the

fall in VDD because the internal analog supply is turned on when VDD > VDD(start). This

function enables the comparators to monitor the voltage on the CP pin and if the supply

voltage VDD falls below VDD(stop).

7.2 Oscillation and timing

7.2.1 Oscillator control

The internal oscillator is a VCO which generates a saw-tooth waveform between the

Vth(CF)max level and 0 V. Capacitor CCF, resistor Rext(RREF) and the voltage on the CI pin

determine the saw-tooth frequency. Rext(RREF) and CCF determine the minimum and

maximum switching frequencies. Their ratio is internally fixed. Two ratios are available,

the ratio between fbridge(max) and fbridge(min) is 2.5 and the ratio between fbridge(max) and

fbridge(bst)min is 4.6. The saw-tooth frequency is twice the half-bridge frequency.

Transistors HS (Q1) and LS (Q2) are switched to conducting at a duty cycle of

approximately 50 %. An overview of the oscillator signal and driver signals is shown in

Figure 8. The oscillator starts oscillating at fbridge(max). The non-overlap time between the

gate driver signals VGLS and VGHS is tno.

voltage

(V)

VCF

0

V(GHS-HBO)

0

VGLS

0

tdch

tno

tno

VHBO

0

Fig 8. Saw-tooth, gate driver and half-bridge output signals

time (s)

001aam766

7.2.2 Combined timing circuit

A combined timing circuit is used to determine the preheat time, ignition enabling time and

overcurrent time (see Figure 9). CCP, Rext(RREF) and the counter comprise the clock

generator circuit. When the timer is not running, CCP is charged to 5 V. The timing circuit

UBA20261_UBA20262

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 10 October 2011

© NXP B.V. 2011. All rights reserved.

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