IS43TR16640A-125KBL データシートの表示（PDF） - Unspecified

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IS43TR16640A-125KBL

128MX8, 64MX16 1Gb DDR3 SDRAM

Unspecified 

IS43TR16640A, IS43TR81280A

16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew

rate. Note for DQ and DM signals, VREF(DC)=VRefDQ(DC). For input only pins except RESET,

VRef(DC)=VRefCA(DC).

17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate.

18. Note for DQ and DM signals, VREF(DC)=VRefDQ(DC). For input only pins except RESET, VRef(DC)=VRefCA(DC).

19. Start of internal write transaction is defined as follows:

20. For BL8 (fixed by MRS and on-the-fly): Rising clock edge 4 clock cycles after WL.

21. For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL.

22. For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.

19. The maximum preamble is bound by tLZ(DQS)max on the left side and tDQSCK(max) on the right side.

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are

in progress, but power-down IDD spec will not be applied until finishing those operations.

21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there

are cases where additional time such as tXPDLL(min) is also required.

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

23. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error

within 64 nCK for all speed bins assuming the maximum sensitivities specified in the “Output Driver Voltage and

Temperature Sensitivity” and “ODT Voltage and Temperature Sensitivity” tables. The appropriate interval between

ZQCS commands can be determined from these tables and other application-specific parameters.

23. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage

(Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. the interval could be defined by the

following formula:

ZQCorrection / [(TSens x Tdriftrate) + (VSens x Vdriftrate)]

, where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and

voltage sensitivities.

For example, if TSens = 1.5%/C, VSens = 0.15%/mV, Tdriftrate = 1 C/sec and Vdriftrate = 15mV/sec, then the interval

between ZQCS commands is calculated as

0.5 / [(1.5x1)+(0.15x15)] = 0.133  128ms

24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following

falling edge.

26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following

rising edge.

27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of

derating to accommodate for the lower altemate threshold of 150mV and another 25ps to account for the earlier

reference point [(175mV - 150mV) / 1V/ns].

28. Pulse width of a input signal is defined as the width between the first crossing of Vref(dc) and the consecutive

crossing of Vref(dc).

29. tDQSL describes the instantaneous differential input low pulse width on DQS - DQS#, as measured from one falling

edge to the next consecutive rising edge.

30. tDQSH describes the instantaneous differential input high pulse width on DQS - DQS#, as measured from one rising

edge to the next consecutive falling edge.

31. tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing

parameter in the application.

32. tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter

in the application.

Integrated Silicon Solution, Inc. – www.issi.com –

61

Rev. 00A

04/16/2012

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