TDA9380 データシートの表示（PDF） - Philips Electronics
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TDA9380 Datasheet PDF : 118 Pages
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Philips Semiconductors
TV signal processor-Teletext decoder with
embedded µ-Controller
Tentative Device Specification
TDA935X/6X/8X PS/N2 series
bytes are grouped into 4 banks of 8 registers, the next 16 bytes above the register banks form a block of bit addressable
memory space. The upper 128 bytes are not allocated for any special area or functions.
7FH
2FH
Bank Select
Bits in PSW
20H
1FH
11 = BANK3
18H
17H
10 = BANK2
10H
0FH
01 = BANK1
08H
07H
00 = BANK0
00H
Fig.6 Lower 128 Bytes of Internal RAM
SFR MEMORY
The Special Function Register (SFR) space is used for port latches, counters/timers, peripheral control, data capture and
display. These registers can only be accessed by direct addressing. Sixteen of the addresses in the SFR space are both
bit and byte addressable. The bit addressable SFRs are those whose address ends in 0H or 8H. A summary of the SFR
map in address order is shown in Table 2.
ADD R/W
Names
80H R/W P0
81H R/W SP
82H R/W DPL
83H R/W DPH
84H R/W IEN1
85H R/W IP1
87H R/W PCON
88H R/W TCON
89H R/W TMOD
8AH R/W TL0
8BH R/W TL1
8CH R/W TH0
8DH R/W TH1
90H R/W P1
91H R/W TP2L
Table 2 SFR Map
BIT7
Reserved
SP<7>
DPL<7>
DPH<7>
-
-
0
TF1
GATE
TL0<7>
TL1<7>
TH0<7>
TH1<7>
P1<7>
TP2L<7>
BIT6
P0<6>
SP<6>
DPL<6>
DPH<6>
-
-
ARD
TR1
C/T
TL0<6>
TL1<6>
TH0<6>
TH1<6>
P1<6>
TP2L<6>
BIT5
P0<5>
SP<5>
DPL<5>
DPH<5>
-
-
RFI
TF0
M1
TL0<5>
TL1<5>
TH0<5>
TH1<5>
Reserved
TP2L<5>
BIT4
Reserved
SP<4>
DPL<4>
DPH<4>
-
-
WLE
TR0
M0
TL0<4>
TL1<4>
TH0<4>
TH1<4>
Reserved
TP2L<4>
BIT3
Reserved
SP<3>
DPL<3>
DPH<3>
-
-
GF1
IE1
GATE
TL0<3>
TL1<3>
TH0<3>
TH1<3>
P1<3>
TP2L<3>
BIT2
Reserved
SP<2>
DPL<2>
DPH<2>
-
-
GF0
IT1
C/T
TL0<2>
TL1<2>
TH0<2>
TH1<2>
P1<2>
TP2L<2>
BIT1
Reserved
SP<1>
DPL<1>
DPH<1>
-
-
PD
IE0
M1
TL0<1>
TL1<1>
TH0<1>
TH1<1>
P1<1>
TP2L<1>
BIT0
Reserved
SP<0>
DPL<0>
DPH<0>
ET2
PT2
IDL
IT0
M0
TL0<0>
TL1<0>
TH0<0>
TH1<0>
P1<0>
TP2L<0>
2001 Jan 18
12
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