TDA9380 データシートの表示（PDF） - Philips Electronics
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TDA9380 Datasheet PDF : 118 Pages
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Philips Semiconductors
TV signal processor-Teletext decoder with
embedded µ-Controller
Tentative Device Specification
TDA935X/6X/8X PS/N2 series
ADD R/W
Names
92H R/W TP2H
93H R/W TP2PR
94H R/W TP2CRL
96H R/W P0CFGA
97H R/W P0CFGB
98H R/W SADB
9CH
R TP2CL
9DH
R TP2CH
9EH R/W P1CFGA
9FH R/W P1CFGB
A0H R/W P2
A6H R/W P2CFGA
A7H R/W P2CFGB
A8H R/W IE
B0H R/W P3
B2H R/W TXT18
B3H R/W TXT19
B4H R/W TXT20
B5H R/W TXT21
B6H
R TXT22
B7H R/W CCLIN
B8H R/W IP
B9H R/W TXT17
BAH
R WSS1
BBH
R WSS2
BCH
R WSS3
BEH
BFH
C0H
R/W P3CFGA
R/W P3CFGB
R/W TXT0
Table 2 SFR Map
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
TP2H<15> TP2H<14> TP2H<13> TP2H<12> TP2H<11> TP2H<10>
TP2H<9>
TP2H<8>
TP2PR<7> TP2PR<6> TP2PR<5> TP2PR<4> TP2PR<3> TP2PR<2> TP2PR<1> TP2PR<0>
-
-
-
-
-
-
TP2CRL<1> TP2CRL<0>
Reserved
P0CFGA<6>
P0CFGA<5>
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved P0CFGB<6> P0CFGB<5> Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
DC_COMP
SAD<3>
SAD<2>
SAD<1>
SAD<0>
TP2CL<7> TP2CL<6> TP2CL<5> TP2CL<4> TP2CL<3> TP2CL<2> TP2CL<1> TP2CL<0>
TP2CH<7> TP2CH<6> TP2CH<5> TP2CH<4> TP2CH<3> TP2CH<2> TP2CH<1> TP2CH<0>
P1CFGA<7>
P1CFGA<6>
Reserved
Reserved
P1CFGA<3>
P1CFGA<2>
P1CFGA<1>
P1CFGA<0>
P1CFGB<7> P1CFGB<6> Reserved
Reserved P1CFGB<3> P1CFGB<2> P1CFGB<1> P1CFGB<0>
Reserved
-
-
-
-
-
-
P2<0>
Reserved
P2CFGA<6>
P2CFGA<5>
P2CFGA<4>
P2CFGA<3>
P2CFGA<2>
P2CFGA<1>
P2CFGA<0>
Reserved P2CFGB<6> P2CFGB<5> P2CFGB<4> P2CFGB<3> P2CFGB<2> P2CFGB<1> P2CFGB<0>
EA
EBUSY
ES2
ECC
ET1
EX1
ET0
EX0
Reserved
Reserved
Reserved
Reserved
P3<3>
P3<2>
P3<1>
P3<0>
NOT<3>
NOT<2>
NOT<1>
NOT<0>
0
0
BS<1>
BS<0>
TEN
TC<2>
TC<1>
TC<0>
0
0
TS<1>
TS<0>
DRCS
OSD
0
ENABLE
PLANES
0
OSD LANG
OSD
OSD
OSD
ENABLE
LAN<2>
LAN<1>
LAN<0>
DISP
LINE<1>
DISP
LINES<0>
CHAR
SIZE<1>
CHAR
SIZE<0>
Reserved
CC ON
I2C PORT0
CC/TXT
GPF1<7>
GPF1<6>
GPF1<5>
GPF1<4>
GPF1<3>
GPF1<2>
GPF1<1>
GPF1<0>
0
0
0
CS<4>
CS<3>
CS<2>
CS<1>
CS<0>
0
PBUSY
PES2
PCC
PT1
PX1
PT0
PX0
0
FORCE
FORCE
FORCE
FORCE
SCREEN
SCREEN
SCREEN
ACQ<1>
ACQ<0>
DISP<1>
DISP<0>
COL<2>
COL<1>
COL<0>
0
0
0
WSS<3:0>
WSS<3>
WSS<2>
WSS<1>
WSS<0>
ERROR
0
0
0
WSS<7:4>
WSS<7>
WSS<6>
WSS<5>
WSS<4>
ERROR
WSS<13:11>
ERROR
WSS<13>
WSS<12>
WSS<11>
WSS<10:8>
ERROR
WSS<10>
WSS<9>
WSS<8>
Reserved
Reserved
Reserved
Reserved
P3CFGA<3>
P3CFGA<2>
P3CFGA<1>
P3CFGA<0>
Reserved
Reserved
Reserved
Reserved P3CFGB<3> P3CFGB<2> P3CFGB<1> P3CFGB<0>
X24 POSN
DISPLAY
X24
AUTO
FRAME
DISABLE
HEADER
ROLL
DISPLAY
STATUS
ROW ONLY
DISABLE
FRAME
VPS ON
INV ON
2001 Jan 18
13
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