TDA9367 データシートの表示（PDF） - Philips Electronics

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TDA9367

TV signal processor-Teletext decoder with embedded micro-Controller

Philips Electronics 

Philips Semiconductors

TV signal processor-Teletext decoder with

embedded µ-Controller

Tentative Device Specification

TDA935X/6X/8X PS/N2 series

ADD R/W

Names

E7H

R CCDAT2

E8H R/W SAD

F0H R/W B

F8H R/W TXT13

FAH R/W XRAMP

FBH R/W ROMBK

FDH

R TEST

FEH

W WDTKEY

FFH R/W WDT

Table 2 SFR Map

BIT7

CCD2<7>

VHI

B<7>

VPS

RECEIVED

XRAMP<7>

STANDBY

TEST<7>

WKEY<7>

WDV<7>

BIT6

CCD2<6>

CH<1>

B<6>

PAGE

CLEARING

XRAMP<6>

IIC_LUT<1>

TEST<6>

WKEY<6>

WDV<6>

BIT5

CCD2<5>

CH<0>

B<5>

525

DISPLAY

XRAMP<5>

IIC_LUT<0>

TEST<5>

WKEY<5>

WDV<5>

BIT4

CCD2<4>

ST

B<4>

525 TEXT

XRAMP<4>

0

TEST<4>

WKEY<4>

WDV<4>

BIT3

CCD2<3>

SAD<7>

B<3>

625 TEXT

XRAMP<3>

0

TEST<3>

WKEY<3>

WDV<3>

BIT2

CCD2<2>

SAD<6>

B<2>

PKT 8/30

XRAMP<2>

0

TEST<2>

WKEY<2>

WDV<2>

BIT1

CCD2<1>

SAD<5>

B<1>

FASTEXT

BIT0

CCD2<0>

SAD<4>

B<0>

0

XRAMP<1> XRAMP<0>

ROMBK<1> ROMBK<0>

TEST<1>

TEST<0>

WKEY<1> WKEY<0>

WDV<1>

WDV<0>

A description of each of the SFR bits is shown in Table 3, The SFRs are in alphabetical order.

Names

ADD

BIT7

BIT6

BIT5

BIT4

BIT3

ACC

E0H

ACC<7>

ACC<6>

ACC<5>

ACC<4>

ACC<3>

ACC<7:0> Accumulator value.

B

F0H

B<7>

B<6>

B<5>

B<4>

B<3>

B<7:0> B Register value.

CCDAT1

D7H CCD1<7> CCD1<6> CCD1<5> CCD1<4> CCD1<3>

CCD1<7:0> Closed Caption first data byte.

CCDAT2

E7H CCD2<7> CCD2<6> CCD2<5> CCD2<4> CCD2<3>

CCD2<7:0> Closed Caption second data byte.

CCLIN

B7H

0

0

0

CS<4>

CS<3>

CS<4:0> Closed Caption Slice line using 525 line number.

DPH

83H

DPH<7>

DPH<6>

DPH<5>

DPH<4>

DPH<3>

DPH<7:0> Data Pointer High byte, used with DPL to address display and auxiliary memory.

DPL

82H

DPL<7>

DPL<6>

DPL<5>

DPL<4>

DPL<3>

DPL<7:0> Data pointer low byte, used with DPH to address display and auxiliary memory.

IE

A8H

EA

EBUSY

ES2

ECC

ET1

EA Disable all interrupts (0), or use individual interrupt enable bits (1).

EBUSY Enable BUSY Interrupt.

ES2 Enable I2C Interrupt.

ECC Enable Closed Caption Interrupt.

Table 3 SFR Bit description

BIT2

ACC<2>

B<2>

CCD1<2>

CCD2<2>

CS<2>

DPH<2>

DPL<2>

EX1

BIT1

ACC<1>

B<1>

CCD1<1>

CCD2<1>

CS<1>

DPH<1>

DPL<1>

ET0

BIT0

ACC<0>

RESET

00H

B<0>

00H

CCD1<0>

00H

CCD2<0>

00H

CS<0>

15H

DPH<0>

00H

DPL<0>

00H

EX0

00H

2001 Jan 18

15

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