TDA9362 データシートの表示（PDF） - Philips Electronics

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TDA9362

TV signal processor-Teletext decoder with embedded micro-Controller

Philips Electronics 

Philips Semiconductors

TV signal processor-Teletext decoder with

embedded µ-Controller

Tentative Device Specification

TDA935X/6X/8X PS/N2 series

Names

ADD

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

STA START flag. When this bit is set in slave mode, the hardware checks the I2C bus and generates a START condition if the bus is free or after the bus

becomes free. If the device operates in master mode it will generate a repeated START condition.

STO STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C bus clears this bit. This bit may also

be set in slave mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C bus, but the hardware releases

the SDA and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware.

SI Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur:

-A START condition is generated in master mode.

-The own slave address has been received during AA=1.

-The general call address has been received while S1ADR.GC and AA=1.

-A data byte has been received or transmitted in master mode (even if arbitration is lost).

-A data byte has been received or transmitted as selected slave.

A STOP or START condition is received as selected slave receiver or transmitter

While the SI flag is set, SCL remains LOW and the serial transfer is suspened.SI must be reset by software.

AA Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions

-Own slave address is received.

-General call address is received(S1ADR.GC=1).

-A data byte is received, while the device is programmed to be a master receiver.

-A data byte is received, while the device is selected slave receiver.

When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received.

S1DAT

DAH DAT<7>

DAT<6>

DAT<5>

DAT<4>

DAT<3>

DAT<2>

DAT<1>

DAT<0>

00H

DAT<7:0> I2C Data.

S1STA

D9H STAT<4>

STAT<3>

STAT<2>

STAT<1>

STAT<0>

0

0

0

F8H

STAT<4:0> I2C Interface Status.

SAD

E8H

VHI

CH<1>

CH<0>

ST

SAD<7>

SAD<6>

SAD<5>

SAD<4>

00H

VHI 0 - Analogue input voltage less than or equal to DAC voltage.

1 - Analogue input voltage greater then DAC voltage.

CH<1:0>

ADC Input channel select.

CH<1:0> = 00,ADC3.

CH<1:0> = 01,ADC0.

CH<1:0> = 10,ADC1.

CH<1:0> = 11,ADC2.

ST Initiate voltage comparison between ADC input Channel and SADB<3:0> value.

Note: Set by Software and reset by Hardware.

SAD<7:4> Most Significant nibble of DAC input word

SADB

98H

0

0

0

DC_COMP SAD<3>

SAD<2>

SAD<1>

SAD<0>

00H

DC_COMP 0 - Disable DC Comparator mode.

1 - Enable DC Comparator mode.

SAD<3:0> 4-bit SAD value.

SP

81H

SP<7>

SP<6>

SP<5>

SP<4>

SP<3>

SP<2>

SP<1>

SP<0>

07H

SP<7> Stack Pointer.

TCON

88H TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00H

TF1 Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine.

Table 3 SFR Bit description

2001 Jan 18

19

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