IRS2608DSPBF データシートの表示（PDF） - International Rectifier

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IRS2608DSPBF

HALF-BRIDGE DRIVER

International Rectifier 

IRS2608DSPbF

Figure 19: Antenna Loops

Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and COM pins. A ceramic 1 µF

ceramic capacitor is suitable for most applications. This component should be placed as close as possible to the pins in

order to reduce parasitic elements.

Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the

switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is

recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to

negative bus rail stray inductance. However, where negative VS spikes remain excessive, further steps may be taken to

reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin and the switch node (see Figure 20),

and in some cases using a clamping diode between COM and VS (see Figure 21). See DT04-4 at www.irf.com for more

detailed information.

Figure 20: VS resistor

Integrated Bootstrap FET limitation

Figure 21: VS clamping diode

The integrated Bootstrap FET functionality has an operational limitation under the following bias conditions applied

to the HVIC:

• VCC pin voltage = 0V

AND

• VS or VB pin voltage > 0

In the absence of a VCC bias, the integrated bootstrap FET voltage blocking capability is compromised and a

current conduction path is created between VCC & VB pins, as illustrated in Fig.22 below, resulting in power loss

and possible damage to the HVIC.

www.irf.com

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