PIC12F1840 データシートの表示（PDF） - Microchip Technology

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PIC12F1840

8-Pin Flash Microcontrollers with XLP Technology

Microchip Technology 

TABLE 3-3: PIC12(L)F1840 MEMORY MAP, BANKS 0-7

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

000h

Core Registers

(Table 3-2)

080h

Core Registers

(Table 3-2)

100h

Core Registers

(Table 3-2)

180h

Core Registers

(Table 3-2)

200h

Core Registers

(Table 3-2)

280h

Core Registers

(Table 3-2)

300h

Core Registers

(Table 3-2)

380h

Core Registers

(Table 3-2)

00Bh

00Ch

00Dh

00Eh

00Fh

010h

011h

012h

013h

014h

015h

016h

017h

018h

019h

01Ah

01Bh

01Ch

01Dh

01Eh

01Fh

020h

06Fh

070h

07Fh

PORTA

—

—

—

—

PIR1

PIR2

—

—

TMR0

TMR1L

TMR1H

T1CON

T1GCON

TMR2

PR2

T2CON

—

CPSCON0

CPSCON1

General

Purpose

Register

80 Bytes

Common RAM

08Bh

08Ch

08Dh

08Eh

08Fh

090h

091h

092h

093h

094h

095h

096h

097h

098h

099h

09Ah

09Bh

09Ch

09Dh

09Eh

09Fh

0A0h

0EFh

0F0h

0FFh

TRISA

—

—

—

—

PIE1

PIE2

—

—

OPTION_REG

PCON

WDTCON

OSCTUNE

OSCCON

OSCSTAT

ADRESL

ADRESH

ADCON0

ADCON1

—

General

Purpose

Register

80 Bytes

Accesses

70h – 7Fh

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

16Fh

170h

17Fh

LATA

—

—

—

—

CM1CON0

CM1CON1

—

—

CMOUT

BORCON

FVRCON

DACCON0

DACCON1

SRCON0

SRCON1

—

APFCON

—

—

General

Purpose

Register

80 Bytes

Accesses

70h – 7Fh

18Bh

20Bh

28Bh

30Bh

38Bh

18Ch

ANSELA

20Ch

WPUA

28Ch

—

30Ch

—

38Ch

—

18Dh

—

20Dh

—

28Dh

—

30Dh

—

38Dh

—

18Eh

—

20Eh

—

28Eh

—

30Eh

—

38Eh

—

18Fh

—

20Fh

—

28Fh

—

30Fh

—

38Fh

—

190h

—

210h

—

290h

—

310h

—

390h

—

191h

EEADRL

211h

SSPBUF

291h

CCPR1L

311h

—

391h

IOCAP

192h

EEADRH

212h

SSPADD

292h

CCPR1H

312h

—

392h

IOCAN

193h

EEDATL

213h SSPMASK 293h CCP1CON 313h

—

393h

IOCAF

194h

EEDATH

214h SSPSTAT 294h PWM1CON 314h

—

394h

—

195h

EECON1

215h

SSPCON

295h

CCP1AS

315h

—

395h

—

196h

EECON2

216h SSPCON2 296h PSTR1CON 316h

—

396h

—

197h VREGCON(1) 217h SSPCON3 297h

—

317h

—

397h

—

198h

—

218h

—

298h

—

318h

—

398h

—

199h

RCREG

219h

—

299h

—

319h

—

399h

—

19Ah

TXREG

21Ah

—

29Ah

—

31Ah

—

39Ah CLKRCON

19Bh

SPBRGL

21Bh

—

29Bh

—

31Bh

—

39Bh

—

19Ch SPBRGH 21Ch

—

29Ch

—

31Ch

—

39Ch

MDCON

19Dh

RCSTA

21Dh

—

29Dh

—

31Dh

—

39Dh

MDSRC

19Eh

TXSTA

21Eh

—

29Eh

—

31Eh

—

39Eh MDCARL

19Fh BAUDCON 21Fh

—

29Fh

—

31Fh

—

39Fh MDCARH

1A0h

220h

2A0h

320h

3A0h

Unimplemented

Read as ‘0’

Unimplemented

Read as ‘0’

Unimplemented

Read as ‘0’

Unimplemented

Read as ‘0’

Unimplemented

Read as ‘0’

1EFh

1F0h

1FFh

Accesses

70h – 7Fh

26Fh

270h

27Fh

Accesses

70h – 7Fh

2EFh

2F0h

2FFh

Accesses

70h – 7Fh

36Fh

370h

37Fh

Accesses

70h – 7Fh

3EFh

3F0h

3FFh

Accesses

70h – 7Fh

Legend:

Note 1:

= Unimplemented data memory locations, read as ‘0’.

Available only on PIC12F1840.

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