KSZ8895MLU(2011) データシートの表示（PDF） - Micrel

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コンポーネント説明

メーカー

KSZ8895MLU
(Rev.:2011)

Integrated 5-Port 10/100 Managed Switch

Micrel 

Micrel, Inc.

KSZ8895MLU

List of Figures

Figure 1. Typical Straight Cable Connection ..................................................................................................................... 20

Figure 2. Typical Crossover Cable Connection ................................................................................................................. 20

Figure 3. Auto-Negotiation ................................................................................................................................................. 22

Figure 4. Destination Address Look-Up Flow Chart (Stage 1)........................................................................................... 26

Figure 5. Destination Address Resolution Flow Chart (Stage 2) ....................................................................................... 27

Figure 6. 802.1p Priority Field Format ............................................................................................................................... 31

Figure 7. Tail Tag Frame Format ....................................................................................................................................... 33

Figure 8. KSZ8895MLU EEPROM Configuration Timing Diagram.................................................................................... 37

Figure 9. SPI Write Data Cycle .......................................................................................................................................... 39

Figure 10. SPI Read Data Cycle .......................................................................................................................................... 39

Figure 11. SPI Multiple Write ............................................................................................................................................... 40

Figure 12. SPI Multiple Read ............................................................................................................................................... 40

Figure 13. EEPROM Interface Input Receive Timing Diagram.......................................................................................... 101

Figure 14. EEPROM Interface Output Transmit Timing Diagram...................................................................................... 101

Figure 15. SNI Input Timing ............................................................................................................................................... 102

Figure 16. SNI Output Timing ............................................................................................................................................ 102

Figure 19. MAC Mode MII Timing  Data Received from MII ............................................................................................ 103

Figure 20. MAC Mode MII Timing Parameters .................................................................................................................. 103

Figure 21. SPI Input Timing ............................................................................................................................................... 104

Figure 22. SPI Output Timing............................................................................................................................................. 105

Figure 23. Auto-Negotiation Timing ................................................................................................................................... 106

Figure 24. Reset Timing..................................................................................................................................................... 107

Figure 25. Recommended Reset Circuit............................................................................................................................ 108

Figure 26. Recommended Circuit for Interfacing with CPU/FPGA Reset.......................................................................... 108

October 2011

6

M9999-100311-1.1

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