NXP Semiconductors
PCA9534
8-bit I2C-bus and SMBus low power I/O port with interrupt
SDA
tBUF
SCL
tr
tLOW
tHD;STA
P
S
tHD;DAT
tf
tHIGH
tSU;DAT
Fig 15. Definition of timing
tHD;STA
tSU;STA
Sr
tSP
tSU;STO
0.7 × VDD
0.3 × VDD
0.7 × VDD
0.3 × VDD
P
002aaa986
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
tSU;STA
SCL
tBUF
SDA
tLOW tHIGH
1 / fSCL
tr
tf
tHD;STA
tSU;DAT tHD;DAT
Rise and fall times refer to VIL and VIH.
Fig 16. I2C-bus timing diagram
tVD;DAT
0.7 × VDD
0.3 × VDD
tVD;ACK tSU;STO
0.7 × VDD
0.3 × VDD
002aab175
PCA9534
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 7 November 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
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