S34ML01G2 データシートの表示（PDF） - Spansion Inc.

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S34ML01G2

Spansion® SLC NAND Flash Memory for Embedded

Spansion Inc. 

Data Sheet

2.3

2.4

2.5

2.6

Data Input

The Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is

serial and timed by the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch

Enable low, Command Latch Enable low, Read Enable high, and Write Protect high and latched on the rising

edge of Write Enable. See Figure 6.3 on page 46 and Table 5.4 on page 42 for details of the timing

requirements.

Data Output

The Data Output bus operation allows data to be read from the memory array and to check the Status

Register content, and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip

Enable low, Write Enable high, Address Latch Enable low, and Command Latch Enable low. See Figure 6.4

on page 47 and Table 5.4 on page 42 for details of the timings requirements.

Write Protect

The Hardware Write Protection is activated when the Write Protect pin is low. In this condition, modify

operations do not start and the content of the memory is not altered. The Write Protect pin is not latched by

Write Enable to ensure the protection even during power up.

Standby

In Standby, the device is deselected, outputs are disabled, and power consumption is reduced.

September 5, 2014 S34ML01G2_04G2_10

Spansion® SLC NAND Flash Memory for Embedded

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