DS2430ATR データシートの表示（PDF） - Maxim Integrated

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DS2430ATR

256-Bit 1-Wire EEPROM

Maxim Integrated 

DS2430A

DESCRIPTION

The DS2430A 256-bit 1-Wire EEPROM identifies and stores relevant information about the product to

which it is associated. This lot or product specific information can be accessed with minimal interface, for

example a single port pin of a microcontroller. The DS2430A consists of a factory-lasered registration

number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (14h) plus

256 bits of user-programmable EEPROM and a 64-bit one-time programmable application register. The

S power to read and write the DS2430A is derived entirely from the 1-Wire® communication line. Data is

N transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return.

The 48-bit serial number that is factory-lasered into each DS2430A provides a guaranteed unique identity

IG that allows for absolute traceability. The TO-92 and TSOC packages provide a compact enclosure that

allows standard assembly equipment to handle the device easily for attachment to printed circuit boards

S or wiring. Typical applications include storage of calibration constants, board identification, and product

DE revision status.

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of

W the DS2430A. The DS2430A has four main data components: 1) 64-bit lasered ROM, 2) 256-bit

E EEPROM data memory with scratchpad, 3) 64-bit one-time programmable application register with

scratchpad and 4) 8-bit status memory. The hierarchical structure of the 1-Wire protocol is shown in

N Figure 2. The bus master must first provide one of the four ROM Function Commands: 1) Read ROM, 2)

Match ROM, 3) Search ROM, 4) Skip ROM. The protocol required for these ROM Function Commands

R is described in Figure 8. After a ROM Function Command is successfully executed, the memory

functions become accessible and the master can provide any one of the four memory function commands.

O The protocol for these memory function commands is described in Figure 6. All data is read and written

F least significant bit first.

D 64-BIT LASERED ROM

E Each DS2430A contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code

(14h). The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (Figure

D 3). The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR

N gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas

E 1-Wire Cyclic Redundancy Check is available in Application Note 27. The shift register bits are

initialized to 0. Then starting with the least significant bit of the family code, one bit at a time is shifted

M in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th

bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits

RECOM of CRC should return the shift register to all 0s.

NOT

1-Wire and iButton are registered trademarks of Maxim Integrated Products, Inc.

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