KSZ8893FQL-FX データシートの表示（PDF） - Micrel
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KSZ8893FQL-FX Datasheet PDF : 117 Pages
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Micrel, Inc.
KSZ8893FQL
Register 119 (0x77): User Defined Register 2 ..................................................................................................... 93
Register 120 (0x78): User Defined Register 3 ..................................................................................................... 93
Indirect Access Registers ........................................................................................................................................... 94
Register 121 (0x79): Indirect Access Control 0 ................................................................................................... 94
Register 122 (0x7A): Indirect Access Control 1 ................................................................................................... 94
Register 123 (0x7B): Indirect Data Register 8 ..................................................................................................... 94
Register 124 (0x7C): Indirect Data Register 7 ..................................................................................................... 94
Register 125 (0x7D): Indirect Data Register 6 ..................................................................................................... 94
Register 126 (0x7E): Indirect Data Register 5 ..................................................................................................... 94
Register 127 (0x7F): Indirect Data Register 4 ..................................................................................................... 94
Register 128 (0x80): Indirect Data Register 3...................................................................................................... 95
Register 129 (0x81): Indirect Data Register 2...................................................................................................... 95
Register 130 (0x82): Indirect Data Register 1...................................................................................................... 95
Register 131 (0x83): Indirect Data Register 0...................................................................................................... 95
Reserved Registers .................................................................................................................................................... 95
Register 132 (0x84): Digital Testing Status 0 ...................................................................................................... 95
Register 133 (0x85): Digital Testing Control 0 ..................................................................................................... 95
Register 134 (0x86): Analog Testing Control 0.................................................................................................... 95
Register 135 (0x87): Analog Testing Control 1.................................................................................................... 95
Register 136 (0x88): Analog Testing Control 2.................................................................................................... 95
Register 137 (0x89): Analog Testing Control 3.................................................................................................... 96
Register 138 (0x8A): Analog Testing Status........................................................................................................ 96
Register 139 (0x8B): Analog Testing Control 4 ................................................................................................... 96
Register 140 (0x8C): QM Debug 1....................................................................................................................... 96
Register 141 (0x8D): QM Debug 2....................................................................................................................... 96
Static MAC Address Table.......................................................................................................................................... 97
VLAN Table................................................................................................................................................................. 99
Dynamic MAC Address Table................................................................................................................................... 100
MIB (Management Information Base) Counters ....................................................................................................... 101
Additional MIB Counter Information ................................................................................................................... 103
Absolute Maximum Ratings(1) ...................................................................................................................................... 104
Operating Ratings(2) ...................................................................................................................................................... 104
Electrical Characteristics(4) .......................................................................................................................................... 104
Timing Diagrams ........................................................................................................................................................... 106
EEPROM Timing ...................................................................................................................................................... 106
SNI Timing ................................................................................................................................................................ 107
MII Timing ................................................................................................................................................................. 108
RMII Timing............................................................................................................................................................... 109
SPI Input Timing ....................................................................................................................................................... 110
SPI Output Timing .................................................................................................................................................... 111
Auto-Negotiation Timing ........................................................................................................................................... 112
October 2007
9
M9999-101607-1.3
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