2SK4092 データシートの表示（PDF） - NEC => Renesas Technology

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2SK4092

N-CHANNEL POWER MOS FET

NEC => Renesas Technology 

2SK4092

ELECTRICAL CHARACTERISTICS (TA = 25°C)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

Zero Gate Voltage Drain Current

IDSS

VDS = 600 V, VGS = 0 V

Gate Leakage Current

IGSS

VGS = ±30 V, VDS = 0 V

Gate to Source Cut-off Voltage

Forward Transfer Admittance Note

Drain to Source On-state Resistance Note

VGS(off)

| yfs |

RDS(on)

VDS = 10 V, ID = 1 mA

VDS = 10 V, ID = 10 A

VGS = 10 V, ID = 10 A

Input Capacitance

Ciss

VDS = 10 V,

Output Capacitance

Coss

VGS = 0 V,

Reverse Transfer Capacitance

Crss

f = 1 MHz

Turn-on Delay Time

td(on)

VDD = 150 V, ID = 10 A,

Rise Time

Turn-off Delay Time

tr

td(off)

VGS = 10 V,

RG = 10 Ω

Fall Time

tf

Total Gate Charge

Gate to Source Charge

Gate to Drain Charge

Body Diode Forward Voltage Note

QG

QGS

QGD

VF(S-D)

VDD = 450 V,

VGS = 10 V,

ID = 21 A

IF = 21 A, VGS = 0 V

Reverse Recovery Time

Reverse Recovery Charge

Note Pulsed

trr

IF = 21 A, VGS = 0 V,

Qrr

di/dt = 100 A/μs

MIN. TYP. MAX. UNIT

10 μA

±100 nA

2.5 3.0 3.5 V

4.0

S

0.34 0.4 Ω

3240

pF

550

pF

3

pF

38

ns

15

ns

58

ns

12

ns

50

nC

24

nC

17

nC

0.9 1.5 V

480

ns

6000

nC

TEST CIRCUIT 1 AVALANCHE CAPABILITY

D.U.T.

RG = 25 Ω

L

PG.

50 Ω

VDD

VGS = 20 → 0 V

ID

VDD

IAS BVDSS

VDS

Starting Tch

TEST CIRCUIT 2 SWITCHING TIME

D.U.T.

RG

PG.

VGS

0

τ

τ = 1 μs

Duty Cycle ≤ 1%

RL

VDD

VGS

VGS

Wave Form

10%

0

VDS

90%

VDS

VDS

0

Wave Form

td(on)

VGS 90%

90%

10% 10%

tr td(off) tf

ton

toff

TEST CIRCUIT 3 GATE CHARGE

D.U.T.

IG = 2 mA

RL

PG.

50 Ω

VDD

2

Data Sheet D18776EJ1V0DS

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