BD82HM55-SLGZS データシートの表示（PDF） - Intel
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BD82HM55-SLGZS Datasheet PDF : 956 Pages
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13.8 Power Management Registers (PM—D31:F0) ....................................................... 524
13.8.1 Power Management PCI Configuration Registers
(PM—D31:F0) ................................................................................... 524
13.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0) ..................................................................... 524
13.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0) ..................................................................... 525
13.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0) ..................................................................... 527
13.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration
Lock Register ...................................................................... 529
13.8.1.5 Chipset Initialization Register 4 (PM—D31:F0) ......................... 530
13.8.1.6 BM_BREAK_EN Register (PM—D31:F0) ................................... 530
13.8.1.7 PMIR—Power Management Initialization Register (PM—D31:F0) . 531
13.8.1.8 GPIO_ROUT—GPIO Routing Control Register
(PM—D31:F0) ..................................................................... 531
13.8.2 APM I/O Decode ................................................................................ 531
13.8.2.1 APM_CNT—Advanced Power Management Control Port Register . 532
13.8.2.2 APM_STS—Advanced Power Management Status Port Register... 532
13.8.3 Power Management I/O Registers ........................................................ 532
13.8.3.1 PM1_STS—Power Management 1 Status Register ..................... 533
13.8.3.2 PM1_EN—Power Management 1 Enable Register ...................... 536
13.8.3.3 PM1_CNT—Power Management 1 Control Register.................... 537
13.8.3.4 PM1_TMR—Power Management 1 Timer Register ..................... 538
13.8.3.5 PM1_TMR—Power Management 1 Timer Register ..................... 538
13.8.3.6 GPE0_STS—General Purpose Event 0 Status Register ............... 539
13.8.3.7 GPE0_EN—General Purpose Event 0 Enables Register ............... 541
13.8.3.8 SMI_EN—SMI Control and Enable Register .............................. 543
13.8.3.9 SMI_STS—SMI Status Register .............................................. 545
13.8.3.10 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register ............... 547
13.8.3.11 ALT_GP_SMI_STS—Alternate GPI SMI Status Register .............. 548
13.8.3.12 UPRWC—USB Per-Port Registers Write Control......................... 548
13.8.3.13 GPE_CNTL—General Purpose Control Register ......................... 549
13.8.3.14 DEVACT_STS—Device Activity Status Register ......................... 550
13.8.3.15 PM2_CNT—Power Management 2 Control Register.................... 550
13.9 System Management TCO Registers ................................................................... 551
13.9.1 TCO_RLD—TCO Timer Reload and Current Value Register ....................... 551
13.9.2 TCO_DAT_IN—TCO Data In Register .................................................... 552
13.9.3 TCO_DAT_OUT—TCO Data Out Register................................................ 552
13.9.4 TCO1_STS—TCO1 Status Register........................................................ 552
13.9.5 TCO2_STS—TCO2 Status Register........................................................ 554
13.9.6 TCO1_CNT—TCO1 Control Register ...................................................... 555
13.9.7 TCO2_CNT—TCO2 Control Register ...................................................... 556
13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers .................................... 556
13.9.9 TCO_WDCNT—TCO Watchdog Control Register ...................................... 557
13.9.10 SW_IRQ_GEN—Software IRQ Generation Register.................................. 557
13.9.11 TCO_TMR—TCO Timer Initial Value Register .......................................... 557
13.10 General Purpose I/O Registers ........................................................................... 558
13.10.1 GPIO_USE_SEL—GPIO Use Select Register............................................ 559
13.10.2 GP_IO_SEL—GPIO Input/Output Select Register .................................... 559
13.10.3 GP_LVL—GPIO Level for Input or Output Register .................................. 560
13.10.4 GPO_BLINK—GPO Blink Enable Register................................................ 560
13.10.5 GP_SER_BLINK—GP Serial Blink Register .............................................. 561
13.10.6 GP_SB_CMDSTS—GP Serial Blink Command
Status Register.................................................................................. 562
13.10.7 GP_SB_DATA—GP Serial Blink Data Register ......................................... 562
13.10.8 GPI_NMI_EN—GPI NMI Enable Register ................................................ 563
13.10.9 GPI_NMI_STS—GPI NMI Status Register ............................................... 563
13.10.10 GPI_INV—GPIO Signal Invert Register .................................................. 563
13.10.11 GPIO_USE_SEL2—GPIO Use Select 2 Register ....................................... 564
13.10.12 GP_IO_SEL2—GPIO Input/Output Select 2 Register ................................ 564
13.10.13 GP_LVL2—GPIO Level for Input or Output 2 Register .............................. 565
13.10.14 GPIO_USE_SEL3—GPIO Use Select 3 Register ....................................... 566
13.10.15 GP_IO_SEL3—GPIO Input/Output Select 3 Register ................................ 567
13.10.16 GP_LVL3—GPIO Level for Input or Output 3 Register .............................. 568
13.10.17 GP_RST_SEL1—GPIO Reset Select Register ........................................... 569
13.10.18 GP_RST_SEL2—GPIO Reset Select Register ........................................... 569
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