MT46V16M16P データシートの表示（PDF） - Micron Technology

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MT46V16M16P

256Mb: x4, x8, x16 DDR SDRAM

Micron Technology 

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-

mable, as shown in Figure 7. The burst length deter-

mines the maximum number of column locations that

can be accessed for a given READ or WRITE command.

Burst lengths of 2, 4, or 8 locations are available for

both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely

selected by A1–Ai when the burst length is set to two,

by A2–Ai when the burst length is set to four, and by

A3-Ai when the burst length is set to eight (where Ai is

the most significant column address bit for a given

configuration). The remaining (least significant)

address bit(s) is (are) used to select the starting loca-

tion within the block. The programmed burst length

applies to both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type, and the

starting column address, as shown in Table 4, Burst

Definition, on page 14.

256Mb: x4, x8, x16

DDR SDRAM

Figure 7: Mode Register Definition

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register (Mx)

0* 0* Operating Mode CAS Latency BT Burst Length

* M14 and M13 (BA1 and BA0)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M2 M1 M0 Burst Length

0 0 0 Reserved

0 01

2

0 10

4

0 11

8

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

M3

Burst Type

0

Sequential

1

Interleaved

M6 M5 M4

000

001

010

011

100

101

110

111

CAS Latency

Reserved

Reserved

2

Reserved

Reserved

Reserved

2.5

Reserved

M12 M11 M10 M9 M8 M7

0 0 0 0 00

0 0 0 0 10

- - - - --

M6-M0

Valid

Valid

-

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

09005aef8076894f

256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN

13

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc.

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