MT46V16M16P-6 データシートの表示（PDF） - Micron Technology

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MT46V16M16P-6

256Mb: x4, x8, x16 DDR SDRAM

Micron Technology 

READs

READ bursts are initiated with a READ command, as

shown in Figure 12 on page 21.

The starting column and bank addresses are pro-

vided with the READ command and auto precharge is

either enabled or disabled for that burst access. If auto

precharge is enabled, the row being accessed is pre-

charged at the completion of the burst.

NOTE: For the READ commands used in the follow-

ing illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element

from the starting column address will be available fol-

lowing the CAS latency after the READ command.

Each subsequent data-out element will be valid nomi-

nally at the next positive or negative clock edge (i.e., at

the next crossing of CK and CK#). Figure 13 on page 22

shows general timing for each possible CAS latency

setting. DQS is driven by the DDR SDRAM along with

output data. The initial LOW state on DQS is known as

the read preamble; the LOW state coincident with the

last data-out element is known as the read postamble.

Upon completion of a burst, assuming no other

commands have been initiated, the DQs will go High-

Z. A detailed explanation of tDQSQ (valid data-out

skew), tQH (data-out window hold), and the valid data

window are depicted in Figure 40 on page 65 and

Figure 41 on page 66. A detailed explanation of

tDQSCK (DQS transition skew to CK) and tAC (data-out

transition skew to CK) is depicted in Figure 42 on

page 67.

Data from any READ burst may be concatenated

with or truncated with data from a subsequent READ

command. In either case, a continuous flow of data

can be maintained. The first data element from the

new burst follows either the last element of a com-

pleted burst or the last desired data element of a longer

burst which is being truncated. The new READ com-

mand should be issued x cycles after the first READ

256Mb: x4, x8, x16

DDR SDRAM

command, where x equals the number of desired data

element pairs (pairs are required by the 2n-prefetch

architecture). This is shown in Figure 14 on page 23. A

READ command can be initiated on any clock cycle

following a previous READ command. Nonconsecutive

read data is illustrated in Figure 15, Nonconsecutive

READ Bursts, on page 24. Full-speed random read

accesses within a page (or pages) can be performed as

shown in Figure 16, Random READ Accesses, on

page 25.

Data from any READ burst may be truncated with a

BURST TERMINATE command, as shown in Figure 17

on page 26. The BURST TERMINATE latency is equal

to the read (CAS) latency; i.e., the BURST TERMINATE

command should be issued x cycles after the READ

command, where x equals the number of desired data

element pairs (pairs are required by the 2n-prefetch

architecture).

Data from any READ burst must be completed or

truncated before a subsequent WRITE command can

be issued. If truncation is necessary, the BURST TER-

MINATE command must be used, as shown in

Figure 18 on page 27. The tDQSS (NOM) case is shown;

the tDQSS (MAX) case has a longer bus idle time.

(tDQSS [MIN] and tDQSS [MAX] are defined in the sec-

tion on WRITEs.)

A READ burst may be followed by, or truncated with,

a PRECHARGE command to the same bank provided

that auto precharge was not activated.

The PRECHARGE command should be issued x

cycles after the READ command, where x equals the

number of desired data element pairs (pairs are

required by the 2n-prefetch architecture). This is

shown in Figure 19 on page 28. Following the PRE-

CHARGE command, a subsequent command to the

same bank cannot be issued until both tRAS and tRP

have been met. Note that part of the row precharge

time is hidden during the access of the last data ele-

ments.

09005aef8076894f

256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc.

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