MICRF002BM データシートの表示（PDF） - Micrel

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MICRF002BM

300-440MHz QwikRadio™ASK Receiver

Micrel 

MICRF002/RF022

CAGC Pin

VDDBB

1.5µA

Compa-

rator

67.5µA

CAGC

Timout

15µA

675µA

VSSBB

Figure 3. CAGC Pin

Figure 3 illustrates the CAGC pin interface circuit. The AGC

control voltage is developed as an integrated current into a

capacitor CAGC. The attack current is nominally 15µA, while

the decay current is a 1/10th scaling of this, nominally 1.5µA,

making the attack/decay time constant ratio a fixed 10:1.

Signal gain of the RF/IF strip inside the IC diminishes as the

voltage at CAGC decreases. Modification of the attack/decay

ratio is possible by adding resistance from the CAGC pin to

either VDDBB or VSSBB, as desired.

Both the push and pull current sources are disabled during

shutdown, which maintains the voltage across CAGC, and

improves recovery time in duty-cycled applications. To fur-

ther improve duty-cycle recovery, both push and pull currents

are increased by 45 times for approximately 10ms after

release of the SHUT pin. This allows rapid recovery of any

voltage droop on CAGC while in shutdown.

DO and WAKEB Pins

VDDBB

Compa-

rator

10µA

DO

10µA

VSSBB

Figure 4. DO and WAKEB Pins

The output stage for DO (digital output) and WAKEB (wakeup

output) is shown in Figure 4. The output is a 10µA push and

10µA pull switched-current stage. This output stage is ca-

pable of driving CMOS loads. An external buffer-driver is

recommended for driving high-capacitance loads.

REFOSC Pin

REFOSC

30pF

Active

Bias

VDDBB

200k

250Ω

Micrel

30pF

VSSBB

30µA

VSSBB

Figure 5. REFOSC Pin

The REFOSC input circuit is shown in Figure 5. Input imped-

ance is high (200kΩ). This is a Colpitts oscillator with internal

30pF capacitors. This input is intended to work with standard

ceramic resonators connected from this pin to the VSSBB

pin, although a crystal may be used when greater frequency

accuracy is required. The nominal dc bias voltage on this pin

is 1.4V.

SEL0, SEL1, SWEN, and SHUT Pins

VDDBB

Q1

VSSBB

SHUT

Q4

Q2

to Internal

Circuits

SEL0,

SEL1,

Q3

SWEN

VSSBB

Figure 6a. SEL0, SEL1, SWEN

VDDBB

Q1

VSSBB

SHUT

Q2

to Internal

Circuits

Q3

VSSBB

Figure 6b. SHUT

Control input circuitry is shown in Figures 6a and 6b. The

standard input is a logic inverter constructed with minimum

geometry MOSFETs (Q2, Q3). P-channel MOSFET Q1 is a

large channel length device which functions essentially as a

“weak” pullup to VDDBB. Typical pullup current is 5µA,

leading to an impedance to the VDDBB supply of typically

1MΩ.

March 2003

13

MICRF002/RF022

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